AMD-K6-2E Datasheet, PDF (115/332 Pages) Advanced Micro Devices – AMD-K6™-2E Embedded Processor

22529B/0—January 2000
Preliminary Information
AMD-K6™-2E Processor Data Sheet
5.15
CACHE# (Cacheable Access)
Pin Attribute
Pin Location
Summary
Driven and Floated
Output
U-03
For reads, CACHE# is asserted to indicate the cacheability of
the current bus cycle. In addition, if the processor samples
KEN # asserted, which indicates the driven address is
cacheable, the cycle is a 32-byte burst read cycle. For write
cycles, CACHE# is asserted to indicate the current bus cycle is a
modified cache-line writeback. KEN # is ignored during
writebacks. If CACHE# is not asserted, or if KEN # is sampled
negated during a read cycle, the cycle is not cacheable and
defaults to a single-transfer cycle.
CACHE# is driven off the same clock edge as ADS# and remains
in the same state until the clock edge on which NA# or the last
expected BRDY# of the cycle is sampled asserted.
CACHE # is floated off the clock edge that BOFF # is sampled
asserted and off the clock edge that the processor asserts HLDA
in recognition of HOLD.
5.16
CLK (Clock)
Pin Attribute
Input
Pin Location
Summary
AK-18
The CLK signal is the bus clock for the processor and is the
reference for all signal timings under normal operation (except
for TDI, TDO, TMS, and TRST#). BF[2:0] determine the internal
frequency multiplier applied to CLK to obtain the processor’s
core operating frequency. See “BF[2:0] (Bus Frequency)” on
page 93 for a list of the processor-to-bus clock ratios.
Sampled
The CLK signal must be stable a minimum of 1.0 ms prior to the
negation of RESET to ensure the proper operation of the
processor. See “CLK Switching Characteristics” on page 267 for
details regarding the CLK specifications.
Chapter 5
Signal Descriptions
97