AMD-K6-2E Datasheet, PDF (61/332 Pages) Advanced Micro Devices – AMD-K6™-2E Embedded Processor

22529B/0—January 2000
Preliminary Information
AMD-K6™-2E Processor Data Sheet
Extended Feature
Enable Register
(EFER)
The extended feature enable register (EFER) contains the
control bits that enable the extended features of the
AMD-K6-2E processor. Figure 34 shows the format of the EFER
register, and Table 6 defines the function of each bit in the
EFER register.
63
4 3 210
DS
EWBEC P C
EE
Reserved
Symbol
Description
Bit
EWBEC
EWBE# Control
3-2
DPE
Data Prefetch Enable
1
SCE
System Call Extension
0
Figure 34. Extended Feature Enable Register (EFER)
Table 6. Extended Feature Enable Register (EFER)Definition
Bit Description
63–4 Reserved
3-2 EWBE# Control
(EWBEC)
1 Data Prefetch Enable
(DPE)
0 System Call Extension
(SCE)
R/W Function
R Writing a 1 to any reserved bit causes a general protection fault to occur. All
reserved bits are always read as 0.
R/W This 2-bit field controls the behavior of the processor with respect to the ordering of
write cycles and the EWBE# signal. EFER[3] and EFER[2] are Global EWBE# Disable
(GEWBED) and Speculative EWBE# Disable (SEWBED), respectively.
R/W DPE must be set to 1 to enable data prefetching (this is the default setting following
reset). If enabled, cache misses initiated by a memory read within a 32-byte cache
line are conditionally followed by cache-line fetches of the other line in the 64-byte
sector.
R/W _{SCE must be set to 1 to enable the usage of the SYSCALL and SYSRET instructions.}
For more information about the EWBEC bits, see “EWBE#
Control” on page 205.
Chapter 3
Software Environment
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