AMD-K6-2E Datasheet, PDF (197/332 Pages) Advanced Micro Devices – AMD-K6™-2E Embedded Processor

22529B/0—January 2000
Preliminary Information
AMD-K6™-2E Processor Data Sheet
7
Power-On Configuration and Initialization
7.1
FLUSH#
BF[2:0]
On power-on, the system logic must reset the AMD-K6-2E
processor by asserting the RESET signal. When the processor
samples RESET asserted, it immediately flushes and initializes
all internal resources and its internal state, including its
pipelines and caches, the floating-point state, the MMX and
3DNow! states, and all registers. Then, the processor jumps to
address FFFF_FFF0h to start instruction execution.
Signals Sampled During the Falling Transition of RESET
FLUSH# is sampled on the falling transition of RESET to
determine if the processor begins normal instruction execution
or enters three-state test mode.
s If FLUSH# is High during the falling transition of RESET,
the processor unconditionally runs its Built-In Self Test
(BIST), performs the normal reset functions, then jumps to
address FFFF_FFF0h to start instruction execution. (See
“Built-In Self-Test (BIST)” on page 227 for more details.)
s If FLUSH# is Low during the falling transition of RESET,
the processor enters three-state test mode. (See
“Three-State Test Mode” on page 228 and “FLUSH# (Cache
Flush)” on page 104 for more details.)
The internal operating frequency of the processor is
determined by the state of the bus frequency signals BF[2:0]
when they are sampled during the falling transition of RESET.
The frequency of the CLK input signal is multiplied internally
by a ratio defined by BF[2:0]. (See “BF[2:0] (Bus Frequency)”
on page 93 for the processor-clock to bus-clock ratios.)
Chapter 7
Power-On Configuration and Initialization
179