AMD-K6-2E Datasheet, PDF (186/332 Pages) Advanced Micro Devices – AMD-K6™-2E Embedded Processor

AMD-K6™-2E Processor Data Sheet
Preliminary Information
22529B/0—January 2000
Interrupt
Acknowledge
In response to recognizing the system’s maskable interrupt
(INTR), the processor drives an interrupt acknowledge cycle at
the next instru cti on boundary. Dur ing an inter rupt
acknowledge cycle, the processor drives a locked pair of read
cycles as shown in Figure 68 on page 169. The first read cycle is
not functional, and the second read cycle returns the interrupt
number on D[7:0] (00h–FFh). Table 27 shows the state of the
signals during an interrupt acknowledge cycle.
Table 27. Interrupt Acknowledge Operation Definition
Processor
Outputs
D/C#
M/IO#
W/R#
BE[7:0]#
A[31:3]
D[63:0]
First Bus Cycle
Low
Low
Low
EFh
0000_0000h
(ignored)
Second Bus Cycle
Low
Low
Low
FEh (low byte enabled)
0000_0000h
Interrupt number expected from interrupt controller
on D[7:0]
The system logic can drive INTR either synchronously or
asynchronously. If it is asserted asynchronously, it must be
asserted for a minimum pulse width of two clocks. To ensure it
is recognized, INTR must remain asserted until an interrupt
acknowledge sequence is complete.
168
Bus Cycles
Chapter 6