AMD-K6-2E Datasheet, PDF (30/332 Pages) Advanced Micro Devices – AMD-K6™-2E Embedded Processor

AMD-K6™-2E Processor Data Sheet
Preliminary Information
22529B/0—January 2000
2.2
Cache
Cache, Instruction Prefetch, and Predecode Bits
The writeback level-one cache on the AMD-K6-2E processor is
organized as a separate 32-Kbyte instruction cache and a
32-Kbyte data cache with two-way set associativity. The cache
line size is 32 bytes and lines are prefetched from main memory
using an efficient pipelined burst transaction.
As the instruction cache is filled, each instruction byte is
analyzed for instruction boundaries using predecoding logic.
Predecoding annotates each instruction byte with information
(5 bits per byte) that later enables the decoders to efficiently
decode multiple instructions simultaneously.
The processor cache design takes advantage of a sectored
organization (see Figure 2). Each sector consists of 64 bytes
configured as two 32-byte cache lines. The two cache lines of a
sector share a common tag but have separate pairs of MESI
(Modified, Exclusive, Shared, Invalid) bits that track the state
of each cache line.
Tag Address
Cache Line 0 Byte 31 Predecode Bits Byte 30 Predecode Bits ........ ........ Byte 0 Predecode Bits MESI Bits
Cache Line 1 Byte 31 Predecode Bits Byte 30 Predecode Bits ........ ........ Byte 0 Predecode Bits MESI Bits
Figure 2. Cache Sector Organization
Prefetching
Two forms of cache misses and associated cache fills can take
place—a tag-miss cache fill and a tag-hit cache fill.
s Tag-miss cache fill—The miss is due to a tag mismatch, in
which case the required cache line is filled from external
memory, and the cache line within the sector that was not
required is marked as invalid.
s Tag-hit cache fill—The address matches the tag, but the
requested cache line is marked as invalid. The required
cache line is filled from external memory, and the cache line
within the sector that is not required remains in the same
cache state.
The AMD-K6-2E processor conditionally performs cache
prefetching which results in the filling of the required cache
line first, and a prefetch of the second cache line making up the
other half of the sector. From the perspective of the external
bus, the two cache-line fills typically appear as two 32-byte
12
Internal Architecture
Chapter 2