AMD-K6-2E Datasheet, PDF (168/332 Pages) Advanced Micro Devices – AMD-K6™-2E Embedded Processor

AMD-K6™-2E Processor Data Sheet
Preliminary Information
22529B/0—January 2000
HOLD-Initiated
Inquire Hit to Shared
or Exclusive Line
Figure 59 on page 151 shows a HOLD-initiated inquire cycle. In
this example, the processor samples HOLD asserted during the
burst memory read cycle. The processor completes the current
cycle (until the last expected BRDY# is sampled asserted),
asserts HLDA, and floats its outputs as described on “Hold and
Hold Acknowledge Cycle” on page 148.
The system logic drives an inquire cycle within the hold
acknowledge cycle. It asserts EADS#, which validates the
inquire address on A[31:5]. If EADS# is sampled asserted
before HOLD is sampled negated, the processor recognizes it as
a valid inquire cycle.
In Figure 59, the processor asserts HIT# and negates HITM# on
the clock edge after the clock edge on which EADS# is sampled
asserted, indicating the current inquire cycle hit a shared or
exclusive cache line. (Shared and exclusive cache lines have not
been modified and do not need to be written back.) During an
inquire cycle, the processor samples INV to determine whether
the addressed cache line found in the processor’s instruction or
data cache transitions to the Invalid state or the Shared state.
In this example, the processor samples INV asserted with
EADS#, which invalidates the cache line.
The system logic can negate HOLD off the same clock edge on
which EADS# is sampled asserted. The processor continues
driving HIT# in the same state until the next inquire cycle.
HITM# is not asserted unless HIT# is asserted.
150
Bus Cycles
Chapter 6