AMD-K6-2E Datasheet, PDF (287/332 Pages) Advanced Micro Devices – AMD-K6™-2E Embedded Processor

22529B/0—January 2000
Preliminary Information
AMD-K6™-2E Processor Data Sheet
t₂
2.0 V
1.5 V
0.8 V
t₅
t₃
t₄
t₁
Figure 89. CLK Waveform
15.4
Valid Delay, Float, Setup, and Hold Timings
Valid Delay and Float
Timing
Setup and Hold
Timing
The maximum valid delay timings are provided to allow a
system designer to determine if setup times to the system logic
can be met. Likewise, the minimum valid delay timings are used
to analyze hold times to the system logic.
s Valid delay and float timings are given for output signals
during functional operation and are given relative to the
rising edge of CLK.
s During boundary-scan testing, valid delay and float timings
for output signals are with respect to the falling edge of
TCK.
The setup and hold time requirements for the AMD-K6-2E
processor input signals must be met by the system logic to
assure the proper operation of the processor.
s The setup and hold timings during functional and
boundary-scan test mode are given relative to the rising
edge of CLK and TCK, respectively.
Chapter 15
Signal Switching Characteristics
269