AMD-K6-2E Datasheet, PDF (244/332 Pages) Advanced Micro Devices – AMD-K6™-2E Embedded Processor

AMD-K6™-2E Processor Data Sheet
Preliminary Information
22529B/0—January 2000
11.8
Exceptions, Interrupts, and Debug in SMM
During an SMI# I/O trap, the exception/interrupt priority of the
AMD-K6-2E processor changes from its normal priority. The
normal priority places the debug traps at a priority higher than
the sampling of the FLUSH# or SMI# signals. However, during
an SMI# I/O trap, the sampling of the FLUSH# or SMI# signals
takes precedence over debug traps.
The processor recognizes the assertion of NMI within SMM
immediately after the completion of an IRET instruction. Once
NMI is recognized within SMM, NMI recognition remains
enabled until SMM is exited, at which point NMI masking is
restored to the state it was in before entering SMM.
226
System Management Mode (SMM)
Chapter 11