AMD-K6-2E Datasheet, PDF (28/332 Pages) Advanced Micro Devices – AMD-K6™-2E Embedded Processor

AMD-K6™-2E Processor Data Sheet
Preliminary Information
22529B/0—January 2000
The three types of decodes have the following characteristics:
s Short decodes—x86 instructions that are less than or equal
to seven bytes long
s Long decodes—x86 instructions less than or equal to 11
bytes long
s Vector decodes—complex x86 instructions
Short and long decodes are processed completely within the
decoders. Vector decodes are started by the decoders and then
completed by fetched sequences from an on-chip ROM. After
decoding, the RISC86 operations are delivered to the scheduler
for dispatching to the execution units.
Scheduler/Instruction
Control Unit
The centralized scheduler or buffer is managed by the ICU. The
ICU buffers and manages up to 24 RISC86 operations at a time.
This equals from 6 to 12 x86 instructions. This buffer size (24) is
perfectly matched to the processor’s six-stage RISC86 pipeline,
four RISC86-operations decode rate, and ten parallel execution
units.
The scheduler accepts as many as four RISC86 operations at a
time from the decoders and retires up to four RISC86
operations per clock cycle. The ICU is capable of
simultaneously issuing up to six RISC86 operations at a time to
the execution units. This consists of the following types of
operations:
s Memory load operation
s Memory store operation
s Complex integer, MMX, or 3DNOW! register operation
s Simple integer register operation
s Floating-point register operation
s Branch condition evaluation
Registers
When managing the RISC86 operations, the ICU uses 69
physical registers contained within the RISC86
microarchitecture.
s Forty-eight of the physical registers are located in a general
register file.
• Twenty-four of these are rename registers.
• The other twenty-four are committed or architectural
registers, consisting of 16 scratch registers and 8 registers
10
Internal Architecture
Chapter 2