AMD-K6-2E Datasheet, PDF (198/332 Pages) Advanced Micro Devices – AMD-K6™-2E Embedded Processor

AMD-K6™-2E Processor Data Sheet
Preliminary Information
22529B/0—January 2000
7.2
RESET Requirements
During the initial power-on reset of the processor, RESET must
remain asserted for a minimum of 1.0 ms after CLK and V_CC
reach specification. (See “CLK Switching Characteristics” on
page 267 for clock specifications. See “Electrical Data” on page
253 for V_CC specifications.)
During a warm reset while CLK and V_CC are within
specification, RESET must remain asserted for a minimum of
15 clocks prior to its negation.
7.3
State of Processor After RESET
Output Signals
Table 29 shows the state of all processor outputs and
bidirectional signals immediately after RESET is sampled
asserted.
Table 29. Output Signal State After RESET
Signal
A[31:3], AP
ADS#, ADSC#
APCHK#
BE[7:0]#
BREQ
CACHE#
D/C#
D[63:0], DP[7:0]
FERR#
HIT#
HITM#
HLDA
State
Floating
High
High
Floating
Low
High
Low
Floating
High
High
High
Low
Signal
LOCK#
M/IO#
PCD
PCHK#
PWT
SCYC
SMIACT#
TDO
VCC2DET
VCC2H/L#
W/R#
–
State
High
Low
Low
High
Low
Low
High
Floating
Low
Low
Low
–
Registers
Table 30 on page 181 shows the state of all architecture
registers and Model-Specific Registers (MSRs) after the
processor has completed its initialization due to the recognition
of the assertion of RESET.
180
Power-On Configuration and Initialization
Chapter 7