AMD-K6-2E Datasheet, PDF (234/332 Pages) Advanced Micro Devices – AMD-K6™-2E Embedded Processor

AMD-K6™-2E Processor Data Sheet
Preliminary Information
22529B/0—January 2000
10.3
Floating-Point and MMX™/3DNow!™ Instruction Compatibility
Registers
The eight 64-bit MMX registers (which are also utilized by
3DNow! instructions) are mapped on the floating-point stack.
This enables backward compatibility with all existing software.
For example, the register saving event that is performed by
operating systems during task switching requires no changes to
the operating system. The same support provided in an
operating system’s interrupt 7 handler (Device Not Available)
for saving and restoring the floating-point registers also
supports saving and restoring the MMX registers.
Exceptions
There are no new exceptions defined for supporting the MMX
and 3DNow! instructions. All exceptions that occur while
decoding or executing an MMX or 3DNow! instruction are
handled in existing exception handlers without modification.
FERR# and IGNNE#
MMX instructions and 3DNow! instructions do not generate
f l o a t i n g -p o i n t e x c e p t i o n s . H oweve r, i f a n u n m a s ke d
floating-point exception is pending, the processor asserts
FERR# at the instruction boundary of the next floating-point
instruction, MMX instruction, 3DNow! instruction or WAIT
instruction.
The sampling of IGNNE# asserted only affects processor
o p e ra t i o n d u r i n g t h e ex e c u t i o n o f a n e r ro r -s e n s i t ive
f l oa t i n g -po i n t i n st r u c ti on , MMX i n st r u c t i on , 3D N ow !
instruction or WAIT instruction when the NE bit in CR0 is
cleared to 0.
216
Floating-Point and Multimedia Execution Units
Chapter 10