AMD-K6-2E Datasheet, PDF (148/332 Pages) Advanced Micro Devices – AMD-K6™-2E Embedded Processor

AMD-K6™-2E Processor Data Sheet
Preliminary Information
22529B/0—January 2000
5.55
Pin Tables by Type
Table 18. Input Pin Types
Name
A20M#¹
AHOLD
BF[2:0]³
BOFF#
BRDY#
BRDYC#
CLK
EADS#
EWBE#⁶
FLUSH#^2,7
HOLD
Type
Asynchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Clock
Synchronous
Synchronous
Asynchronous
Synchronous
Name
IGNNE#¹
INIT²
INTR¹
INV
KEN#
NA#
NMI²
RESET^4,5
SMI#²
STPCLK#¹
WB/WT#
Type
Asynchronous
Asynchronous
Asynchronous
Synchronous
Synchronous
Synchronous
Asynchronous
Asynchronous
Asynchronous
Asynchronous
Synchronous
Notes:
1. These level-sensitive signals can be asserted synchronously or asynchronously. To be sampled on a specific clock edge, setup
and hold times must be met. If asserted asynchronously, they must be asserted for a minimum pulse width of two clocks.
2. These edge-sensitive signals can be asserted synchronously or asynchronously. To be sampled on a specific clock edge, setup
and hold times must be met. If asserted asynchronously, they must have been negated at least two clocks prior to assertion and
must remain asserted at least two clocks.
3. BF[2:0] are sampled during the falling transition of RESET. They must meet a minimum setup time of 1.0 ms and a minimum
hold time of two clocks relative to the negation of RESET.
4. During the initial power-on reset of the processor, RESET must remain asserted for a minimum of 1.0 ms after CLK and V_CC
reach specification before it is negated.
5. During a warm reset, while CLK and V_CC are within their specification, RESET must remain asserted for a minimum of 15 clocks
prior to its negation.
6. When EFER[3] is 1, EWBE# is ignored by the processor.
7. FLUSH# is also sampled during the falling transition of RESET and can be asserted synchronously or asynchronously. To be
sampled on a specific clock edge, setup and hold times must be met relative to the clock edge before the clock edge on which
RESET is sampled negated. If asserted asynchronously, FLUSH# must meet a minimum setup and hold time of two clocks
relative to the negation of RESET.
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Signal Descriptions
Chapter 5