AMD-K6-2E Datasheet, PDF (216/332 Pages) Advanced Micro Devices – AMD-K6™-2E Embedded Processor

AMD-K6™-2E Processor Data Sheet
Preliminary Information
22529B/0—January 2000
8.9
Cache States
Table 34 shows all the possible cache-line states before and
after program-generated accesses to individual cache lines. The
table includes the correspondence between MESI states and
Writethrough or Writeback states for lines in the data cache.
Table 34. Data Cache States for Read and Write Accesses
Type
Cache State Before
Access
Cache
Read
Read miss
Invalid
Invalid
Read hit
Exclusive
Modified
Shared
Invalid
Cache
Write
Invalid
Write miss
Invalid
Write hit
Exclusive or modified
Shared
Cache State After Access
Access Type¹
MESI State²
Writeback/
Writethrough State
Single read from bus
Invalid
Not applicable or none
Burst read from bus, fill
cache³
Shared or
exclusive⁴
Writethrough or writeback⁴
Not applicable or none Exclusive
Writeback
Not applicable or none Modified
Writeback
Not applicable or none Shared
Writethrough
Single write to bus⁵
Invalid
Not applicable or none
Burst read from bus, fill
cache, write to cache⁶
Modified⁷
Not applicable or none
Burst read from bus, fill
cache, write to cache,
single write to bus⁶
Shared⁸
Not applicable or none
Write to cache
Modified
Writeback
Write to cache, single write Shared or
to bus
exclusive⁴
Writethrough or writeback⁴
Notes:
1. Single read, single write, cache update, and writethrough = 1 to 8 bytes. Line fill = 32-byte burst read.
2. The final MESI state assumes that the state of the WB/WT# signal remains the same for all accesses to a particular cache line.
3. If CACHE# is driven Low and KEN# is sampled asserted.
4. If PWT is driven Low and WB/WT# is sampled High, the line is cached in the exclusive (writeback) state. If PWT is driven High or
WB/WT# is sampled Low, the line is cached in the shared (writethrough) state.
5. Assumes the write allocate conditions as specified in “Write Allocate” on page 192 are not met.
6. Assumes the write allocate conditions as specified in “Write Allocate” on page 192 are met.
7. Assumes PWT is driven Low and WB/WT# is sampled High.
8. Assumes PWT is driven High or WB/WT # is sampled Low.
198
Cache Organization
Chapter 8