AMD-K6-2E Datasheet, PDF (225/332 Pages) Advanced Micro Devices – AMD-K6™-2E Embedded Processor

22529B/0—January 2000
Preliminary Information
AMD-K6™-2E Processor Data Sheet
Table 37 summarizes the three settings of the EWBEC field for
the EFER register, along with the effect of write ordering and
performance. For more information on the EFER register, see
“Extended Feature Enable Register (EFER)” on page 43.
Table 37. EWBEC Settings
EFER[3]
(GEWBED)
EFER[2]
(SEWBED)
Write Ordering
Performance
1
0 or 1 None
Best
0
1
All except UC/WC Close-to-Best
0
0
All
Slowest
9.2
Memory Type Range Registers
The AMD-K6-2E processor provides two variable-range Memory
Type Range registers (MTRRs), MTRR0 and MTRR1, each of
which specifies a range of memory. Each range can be defined
as one of the following memory types:
s Uncacheable (UC) Memory—Memory read cycles are
sourced directly from the specified memory address and the
processor does not allocate a cache line. Memory write
cycles are targeted at the specified memory address and a
write allocation does not occur.
s Write-Combining (WC) Memory—Memory read cycles are
sourced directly from the specified memory address and the
processor does not allocate a cache line. The processor
conditionally combines data from multiple noncacheable
write cycles that are addressed within this range into a
merge buffer. Merging multiple write cycles into a single
write cycle reduces processor bus utilization and processor
stalls, thereby increasing the overall system performance.
This memory type is applicable for linear video frame
buffers.
Chapter 9
Write Merge Buffer
207