AMD-K6-2E Datasheet, PDF (291/332 Pages) Advanced Micro Devices – AMD-K6™-2E Embedded Processor

22529B/0—January 2000
Preliminary Information
AMD-K6™-2E Processor Data Sheet
Table 59. Input Setup and Hold Timings for 100-MHz Bus Operation (continued)
Symbol
t₇₂₂
t₇₃₂
t₇₄₁
t₇₅₁
t₇₆
t₇₇
t₇₈
t₇₉
t₈₀
t₈₁
t₈₂₂
t₈₃₂
t₈₄₂
t₈₅₂
t₈₆₁
t₈₇₁
t₈₈
t₈₉
Parameter Description
INIT Setup Time
INIT Hold Time
INTR Setup Time
INTR Hold Time
INV Setup Time
INV Hold Time
KEN# Setup Time
KEN# Hold Time
NA# Setup Time
NA# Hold Time
NMI Setup Time
NMI Hold Time
SMI# Setup Time
SMI# Hold Time
STPCLK# Setup Time
STPCLK# Hold Time
WB/WT# Setup Time
WB/WT# Hold Time
Preliminary Data
Min
Max
1.7 ns
1.0 ns
1.7 ns
1.0 ns
1.7 ns
1.0 ns
3.0 ns
1.0 ns
1.7 ns
1.0 ns
1.7 ns
1.0 ns
1.7 ns
1.0 ns
1.7 ns
1.0 ns
1.7 ns
1.0 ns
Figure
93
93
93
93
93
93
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93
93
93
93
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93
93
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93
Notes:
1. These level-sensitive signals can be asserted synchronously or asynchronously. To be sampled on a specific clock edge, setup
and hold times must be met. If asserted asynchronously, they must be asserted for a minimum pulse width of two clocks.
2. These edge-sensitive signals can be asserted synchronously or asynchronously. To be sampled on a specific clock edge, setup
and hold times must be met. If asserted asynchronously, they must have been negated at least two clocks prior to assertion and
must remain asserted at least two clocks.
Chapter 15
Signal Switching Characteristics
273