AMD-K6-2E Datasheet, PDF (106/332 Pages) Advanced Micro Devices – AMD-K6™-2E Embedded Processor

AMD-K6™-2E Processor Data Sheet
Preliminary Information
22529B/0—January 2000
5.4
ADS# (Address Strobe)
Pin Attribute
Pin Location
Summary
Output
AJ-05
The assertion of ADS # indicates the beginning of a new bus
cycle. The address bus and all cycle definition signals
corresponding to this bus cycle are driven valid off the same
clock edge as ADS#.
Driven and Floated
ADS # is asserted for one clock at the beginning of each bus
cycle. For non-pipelined cycles, ADS# can be asserted as early
as the clock edge after the clock edge on which the last
expected BRDY# of the cycle is sampled asserted, resulting in a
single idle state between cycles. For pipelined cycles if the
processor is prepared to start a new cycle, ADS # can be asserted
as early as one clock edge after NA# is sampled asserted.
If AHOLD is sampled asserted, ADS# is only driven in order to
perform a writeback cycle due to an inquire cycle that hits a
modified cache line.
The processor floats ADS # off the clock edge that BOFF # is
sampled asserted and off the clock edge that the processor
asserts HLDA in recognition of HOLD.
5.5
ADSC# (Address Strobe Copy)
Pin Attribute
Pin Location
Output
AM-02
Summary
ADSC # has the identical function and timing as ADS#. In the
event ADS# becomes too heavily loaded due to a large fanout in
a system, ADSC # can be used to split the load across two
outputs, which can improve system timing.
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Signal Descriptions
Chapter 5