AMD-K6-2E Datasheet, PDF (10/332 Pages) Advanced Micro Devices – AMD-K6™-2E Embedded Processor

AMD-K6™-2E Processor Data Sheet
Preliminary Information
22529B/0—January 2000
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Page Directory Entry 4-Kbyte Page Table (PDE) ........51
Page Directory Entry 4-Mbyte Page Table (PDE) .......51
Page Table Entry (PTE)..................................................52
Application Segment Descriptor ...................................53
System Segment Descriptor ...........................................54
Gate Descriptor ...............................................................55
Waveform Definitions...................................................134
Bus State Machine Diagram .........................................135
Non-Pipelined Single-Transfer Memory
Read/Write and Write Delayed by EWBE# ................139
Misaligned Single-Transfer Memory
Read and Write..............................................................141
Burst Reads and Pipelined Burst Reads .....................143
Burst Writeback due to Cache-Line Replacement.....145
Basic I/O Read and Write .............................................146
Misaligned I/O Transfer................................................147
Basic HOLD/HLDA Operation .....................................149
HOLD-Initiated Inquire Hit to Shared
or Exclusive Line...........................................................151
HOLD-Initiated Inquire Hit to Modified Line............153
AHOLD-Initiated Inquire Miss ....................................155
AHOLD-Initiated Inquire Hit to Shared
or Exclusive Line...........................................................157
AHOLD-Initiated Inquire Hit to Modified Line.........159
AHOLD Restriction.......................................................161
BOFF# Timing................................................................163
Basic Locked Operation................................................165
Locked Operation with BOFF# Intervention..............167
Interrupt Acknowledge Operation ..............................169
Basic Special Bus Cycle (Halt Cycle) ..........................171
Shutdown Cycle .............................................................172
Stop Grant and Stop Clock Modes, Part 1 ..................174
Stop Grant and Stop Clock Modes, Part 2 ..................175
INIT-Initiated Transition from Protected Mode
to Real Mode..................................................................177
Cache Organization .......................................................185
Cache Sector Organization ...........................................186
Write Handling Control Register (WHCR).................194
Write Allocate Logic Mechanisms and Conditions ....195
Page Flush/Invalidate Register (PFIR).......................200
UC/WC Cacheability Control Register (UWCCR) .....208
External Logic for Supporting Floating-Point
Exceptions ...................................................................... 215
SMM Memory.................................................................218
TAP State Diagram .......................................................237
Debug Register DR7 .....................................................241
Debug Register DR6 .....................................................242
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List of Figures