AMD-K6-2E Datasheet, PDF (220/332 Pages) Advanced Micro Devices – AMD-K6™-2E Embedded Processor

AMD-K6™-2E Processor Data Sheet
Preliminary Information
22529B/0—January 2000
Table 35. Cache States for Inquire Cycles, Snoops, Flushes, and Invalidation
Type of Operation
Cache State
Before Operation
Memory Access
Inquire Cycle
Shared or exclusive Not applicable or none
Modified
Writeback to bus
Internal Snoop
Shared or exclusive
Modified
Not applicable or none
Writeback to bus
FLUSH# Signal
Shared or
exclusive
Not applicable or none
Modified
Writeback to bus
PFIR
(F/I = 0)
Shared or exclusive
Modified
Not applicable or none
Writeback to bus
PFIR
(F/I = 1)
Not applicable or none Not applicable or none
Shared or exclusive
WBINVD Instruction
Modified
Not applicable or none
Writeback to bus
INVD Instruction Not applicable or none Not applicable or none
Notes:
All writebacks are 32-byte burst write cycles.
Cache State After Operation
MESI State
INV=0
INV=1
INV=0
INV=1
Shared
Invalid
Shared
Invalid
Writeback/
Writethrough State
Writethrough
Invalid
Writethrough
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
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Cache Organization
Chapter 8