AMD-K6-2E Datasheet, PDF (38/332 Pages) Advanced Micro Devices – AMD-K6™-2E Embedded Processor

AMD-K6™-2E Processor Data Sheet
Preliminary Information
22529B/0—January 2000
Scheduler
Buffer
(24 RISC86^® Operations)
Issue Bus
for the
Register X
Execution
Pipeline
Issue Bus
for the
Register Y
Execution
Pipeline
Integer X
ALU
MMXÉ
ALU
MMX/
3DNow!É
Multiplier
Figure 6. Register X and Y Functional Units
MMX
Shifter
3DNow!
ALU
MMX
ALU
Integer Y
ALU
The branch condition unit is separate from the branch
prediction logic in that it resolves conditional branches such as
JCC and LOOP after the branch condition has been evaluated.
2.6
Branch-Prediction Logic
Sophisticated branch logic that can minimize or hide the impact
of changes in program flow is designed into the AMD-K6-2E
processor. Branches in x86 code fit into two categories:
s Unconditional branches always change program flow (that is,
the branches are always taken)
s Conditional branches may or may not divert program flow
(that is, the branches are taken or not-taken). When a
conditional branch is not taken, the processor simply
continues decoding and executing the next instructions in
memory.
20
Internal Architecture
Chapter 2