AMD-K6-2E Datasheet, PDF (218/332 Pages) Advanced Micro Devices – AMD-K6™-2E Embedded Processor

AMD-K6™-2E Processor Data Sheet
Preliminary Information
22529B/0—January 2000
FLUSH#
Page Flush/Invalidate
Register (PFIR)
cache during read misses to its instruction cache. Table 35
summarizes the actions taken during this internal snooping.
If an internal snoop hits its target, the processor does the
following:
s Data Cache Snoop During an Instruction-Cache Read
Miss—If modified, the line in the data cache is written back
on the system bus to external memory. Regardless of its
state, the data-cache line is invalidated and the instruction
cache performs a burst read cycle from external memory.
s Instruction Cache Snoop During a Data-Cache Miss—The
line in the instruction cache is marked invalid, and the
data-cache read or write is performed from memory.
In response to sampling FLUSH# asserted, the processor writes
back any data cache lines that are in the Modified state and
then marks all lines in the instruction and data caches as
invalid.
The AMD-K6-2E processor contains the page flush/invalidate
register (PFIR) (see Figure 78) that allows cache invalidation
and optional flushing of a specific 4-Kbyte page from the linear
address space. When the PFIR is written to (using the WRMSR
instruction), the invalidation and the flushing (optional) begin.
The total amount of cache in the AMD-K6-2E processor is 64
Kbytes. Using this register can result in a much lower cycle
count for flushing particular pages versus flushing the entire
cache.
63
32 31
LINPAGE
Reserved
Symbol
LINPAGE
PF
F/I
Description
20-bit Linear Page Address
Page Fault Occurred
Flush/Invalidate Command
Bit
31-12
8
0
Figure 78. Page Flush/Invalidate Register (PFIR)—MSR C000_0088h
12 11 9 8 7
10
P
F
F
/
I
200
Cache Organization
Chapter 8