AMD-K6-2E Datasheet, PDF (64/332 Pages) Advanced Micro Devices – AMD-K6™-2E Embedded Processor

AMD-K6™-2E Processor Data Sheet
Preliminary Information
22529B/0—January 2000
Page Flush/Invalidate
Register (PFIR)
The AMD-K6-2E processor contains the Page Flush/Invalidate
Register (PFIR) (see Figure 39) that allows cache invalidation
and optional flushing of a specific 4-Kbyte page from the linear
address space. Using this register can result in a much lower
cycle count for flushing particular pages versus flushing the
entire cache. When the PFIR is written to (using the WRMSR
instruction), the invalidation and, optionally, the flushing
begins.
63
32 31
12 11 9 8 7
10
LINPAGE
P
F
F
/
I
Reserved
Symbol
LINPAGE
PF
F/I
Description
20-bit Linear Page Address
Page Fault Occurred
Flush/Invalidate Command
Bit
31-12
8
0
Figure 39. Page Flush/Invalidate Register (PFIR)
46
Software Environment
Chapter 3