AMD-K6-2E Datasheet, PDF (250/332 Pages) Advanced Micro Devices – AMD-K6™-2E Embedded Processor

AMD-K6™-2E Processor Data Sheet
Preliminary Information
22529B/0—January 2000
The total number of bits that comprise the BSR is 281. Table 45
on page 233 lists the order of these bits, where TDI is the input
to bit 280, and TDO is driven from the output of bit 0. The
entries listed as pin_E (where pin is an output or bidirectional
signal) are the enable bits.
If the BSR is the register selected by the current instruction
and the TAP controller is in the Capture-DR state, the processor
loads the BSR shift register as follows:
s If the current instruction is SAMPLE/PRELOAD, then the
current state of each input, output, and bidirectional pin is
loaded. A bidirectional pin is treated as an output if its
enable bit equals 1, and it is treated as an input if its enable
bit equals 0.
s If the current instruction is EXTEST, then the current state
of each input pin is loaded. A bidirectional pin is treated as
an input, regardless of the state of its enable.
While in the Shift-DR state, the BSR shift register is serially
shifted toward the TDO pin. During the shift, bit 280 of the BSR
is loaded from the TDI pin.
The BSR output register is loaded with the contents of the BSR
shift register in the Update-DR state. If the current instruction
is EXTEST, the processor’s output pins, as well as those
bidirectional pins that are enabled as outputs, are driven with
their corresponding values from the BSR output register.
232
Test and Debug
Chapter 12