AMD-K6-2E Datasheet, PDF (65/332 Pages) Advanced Micro Devices – AMD-K6™-2E Embedded Processor

22529B/0—January 2000
Preliminary Information
AMD-K6™-2E Processor Data Sheet
3.3
Memory Management Registers
The AMD-K6-2E processor controls segmented memory
management with the registers listed in Table 8. Figure 40
shows the formats of the memory management registers.
Table 8. Memory Management Registers
Register Name
Global Descriptor Table Register
Interrupt Descriptor Table Register
Local Descriptor Table Register
Task Register
Function
Contains a pointer to the base of the global descriptor table
Contains a pointer to the base of the interrupt descriptor table
Contains a pointer to the local descriptor table of the current task
Contains a pointer to the task state segment of the current task
Global and Interrupt Descriptor Table Registers
47
16 15
0
32-Bit Linear Base Address
16-Bit Limit
Local Descriptor Table Register and Task Register
15
0
Selector
63
32-Bit Linear Base Address
32 31
0
32-Bit Limit
15
0
Attributes
Figure 40. Memory Management Registers
Chapter 3
Software Environment
47