PIC18F6525_13 Datasheet, PDF (98/400 Pages) Microchip Technology – 64/80-Pin High-Performance, 64-Kbyte Enhanced Flash Microcontrollers with A/D

PIC18F6525/6621/8525/8621
9.4 IPR Registers
The IPR registers contain the individual priority bits for
the peripheral interrupts. Due to the number of
peripheral interrupt sources, there are three Peripheral
Interrupt Priority registers (IPR1, IPR2 and IPR3). The
operation of the priority bits requires that the Interrupt
Priority Enable (IPEN) bit be set.
REGISTER 9-10:
IPR1: PERIPHERAL INTERRUPT PRIORITY REGISTER 1
R/W-1
PSPIP⁽¹⁾
R/W-1
ADIP
R/W-1
RC1IP
R/W-1
TX1IP
R/W-1
SSPIP
R/W-1
CCP1IP
bit 7
R/W-1
TMR2IP
R/W-1
TMR1IP
bit 0
bit 7
PSPIP: Parallel Slave Port Read/Write Interrupt Priority bit⁽¹⁾
1 = High priority
0 = Low priority
Note: Enabled only in Microcontroller mode for PIC18F8525/8621 devices.
bit 6
ADIP: A/D Converter Interrupt Priority bit
1 = High priority
0 = Low priority
bit 5
RC1IP: USART1 Receive Interrupt Priority bit
1 = High priority
0 = Low priority
bit 4
TX1IP: USART1 Transmit Interrupt Priority bit
1 = High priority
0 = Low priority
bit 3
SSPIP: Master Synchronous Serial Port Interrupt Priority bit
1 = High priority
0 = Low priority
bit 2
CCP1IP: ECCP1 Interrupt Priority bit
1 = High priority
0 = Low priority
bit 1
TMR2IP: TMR2 to PR2 Match Interrupt Priority bit
1 = High priority
0 = Low priority
bit 0
TMR1IP: TMR1 Overflow Interrupt Priority bit
1 = High priority
0 = Low priority
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
DS39612C-page 98
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