PIC18F6525_13 Datasheet, PDF (385/400 Pages) Microchip Technology – 64/80-Pin High-Performance, 64-Kbyte Enhanced Flash Microcontrollers with A/D

PIC18F6525/6621/8525/8621
Timer3....................................................................... 144
Timer3 (16-Bit Read/Write Mode) ............................. 144
Timer4....................................................................... 148
Watchdog Timer........................................................ 268
BN ..................................................................................... 284
BNC .................................................................................. 285
BNN .................................................................................. 285
BNOV ................................................................................ 286
BNZ ................................................................................... 286
BOR. See Brown-out Reset.
BOV .................................................................................. 289
BRA................................................................................... 287
Break Character (12-Bit) Transmit and Receive ............... 226
BRG. See Baud Rate Generator.
Brown-out Reset (BOR) .............................................. 30, 259
BSF ................................................................................... 287
BTFSC .............................................................................. 288
BTFSS .............................................................................. 288
BTG................................................................................... 289
BZ ..................................................................................... 290
C
C Compilers
MPLAB C17 .............................................................. 318
MPLAB C18 .............................................................. 318
MPLAB C30 .............................................................. 318
CALL ................................................................................. 290
Capture (CCP Module) ..................................................... 151
Associated Registers ................................................ 153
CCP Pin Configuration.............................................. 151
CCPR4H:CCPR4L Registers.................................... 151
Software Interrupt ..................................................... 151
Timer1/Timer3 Mode Selection................................. 151
Capture (ECCP Module) ................................................... 160
Capture/Compare/PWM (CCP)......................................... 149
Capture Mode. See Capture.
CCP Mode and Timer Resources ............................. 150
CCPRxH Register ..................................................... 150
CCPRxL Register...................................................... 150
Compare Mode. See Compare.
Interconnect Configurations ...................................... 150
Module Configuration................................................ 150
PWM Mode. See PWM.
Clocking Scheme/Instruction Cycle .................................... 44
CLRF................................................................................. 291
CLRWDT........................................................................... 291
Code Examples
16 x 16 Signed Multiply Routine ................................. 86
16 x 16 Unsigned Multiply Routine ............................. 86
8 x 8 Signed Multiply Routine ..................................... 85
8 x 8 Unsigned Multiply Routine ................................. 85
Changing Between Capture Prescalers.................... 151
Computed GOTO Using an Offset Value.................... 46
Data EEPROM Read .................................................. 81
Data EEPROM Refresh Routine................................. 82
Data EEPROM Write .................................................. 81
Erasing a Flash Program Memory Row ...................... 66
Fast Register Stack..................................................... 44
How to Clear RAM (Bank 1) Using
Indirect Addressing ............................................. 56
Implementing a Real-Time Clock Using a
Timer1 Interrupt Service ................................... 138
Initializing PORTA..................................................... 103
Initializing PORTB..................................................... 106
Initializing PORTC..................................................... 109
Initializing PORTD..................................................... 111
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Initializing PORTE .................................................... 114
Initializing PORTF..................................................... 117
Initializing PORTG .................................................... 120
Initializing PORTH .................................................... 122
Initializing PORTJ ..................................................... 125
Loading the SSPBUF (SSPSR) Register ................. 176
Reading a Flash Program Memory Word ................... 65
Saving STATUS, WREG and
BSR Registers in RAM ..................................... 102
Writing to Flash Program Memory........................ 68–69
Code Protection ........................................................ 259, 270
Associated Registers................................................ 271
Configuration Register Protection............................. 273
Data EEPROM ......................................................... 273
Program Memory...................................................... 271
COMF ............................................................................... 292
Comparator....................................................................... 243
Analog Input Connection Considerations ................. 247
Associated Registers................................................ 248
Configuration ............................................................ 244
Effects of a Reset ..................................................... 247
Interrupts .................................................................. 246
Operation.................................................................. 245
Operation During Sleep ............................................ 247
Outputs ..................................................................... 245
Reference ................................................................. 245
External Signal ................................................. 245
Internal Signal .................................................. 245
Response Time ........................................................ 245
Comparator Specifications................................................ 332
Comparator Voltage Reference ........................................ 249
Accuracy and Error................................................... 250
Associated Registers................................................ 251
Configuring ............................................................... 249
Connection Considerations ...................................... 250
Effects of a Reset ..................................................... 250
Operation During Sleep ............................................ 250
Compare (CCP Module) ................................................... 152
Associated Registers................................................ 153
CCP Pin Configuration ............................................. 152
CCPR1 Register ....................................................... 152
Software Interrupt ..................................................... 152
Special Event Trigger ............................................... 152
Timer1/Timer3 Mode Selection ................................ 152
Compare (ECCP Module)................................................. 160
Special Event Trigger ............................... 137, 145, 160
Configuration Bits ............................................................. 259
Context Saving During Interrupts...................................... 102
Control Registers
EECON1 and EECON2 .............................................. 62
TABLAT (Table Latch) Register ................................. 64
TBLPTR (Table Pointer) Register............................... 64
Conversion Considerations............................................... 378
CPFSEQ ........................................................................... 292
CPFSGT ........................................................................... 293
CPFSLT ............................................................................ 293
D
Data EEPROM Memory...................................................... 79
Associated Registers.................................................. 83
EEADR Register......................................................... 79
EEADRH Register ...................................................... 79
EECON1 Register ...................................................... 79
EECON2 Register ...................................................... 79
Operation During Code-Protect .................................. 82
Protection Against Spurious Write.............................. 82
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