PIC18F6525_13 Datasheet, PDF (172/400 Pages) Microchip Technology – 64/80-Pin High-Performance, 64-Kbyte Enhanced Flash Microcontrollers with A/D

PIC18F6525/6621/8525/8621
TABLE 17-5: REGISTERS ASSOCIATED WITH ECCP MODULES AND TIMER1 TO TIMER4
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Value on
all other
Resets
INTCON GIE/GIEH PEIE/GIEL TMR0IE
INT0IE
RBIE
TMR0IF INT0IF
RBIF 0000 000x 0000 000u
RCON
PIR1
PIE1
IPR1
IPEN
PSPIF⁽¹⁾
PSPIE⁽¹⁾
PSPIP⁽¹⁾
—
ADIF
ADIE
ADIP
—
RC1IF
RC1IE
RC1IP
RI
TX1IF
TX1IE
TX1IP
TO
SSPIF
SSPIE
SSPIP
PD
CCP1IF
CCP1IE
CCP1IP
POR
TMR2IF
TMR2IE
TMR2IP
BOR
TMR1IF
TMR1IE
TMR1IP
0--1 11qq 0--q qquu
0000 0000 0000 0000
0000 0000 0000 0000
1111 1111 1111 1111
PIR2
—
CMIF
—
EEIF
BCLIF
LVDIF TMR3IF CCP2IF -0-0 0000 ---0 0000
PIE2
—
CMIE
—
EEIE
BCLIE
LVDIE TMR3IE CCP2IE -0-0 0000 ---0 0000
IPR2
—
CMIP
—
EEIP
BCLIP
LVDIP TMR3IP CCP2IP -1-1 1111 ---1 1111
PIR3
—
—
RC2IF
TX2IF
TMR4IF CCP5IF CCP4IF CCP3IF --00 0000 --00 0000
PIE3
—
—
RC2IE
TX2IE
TMR4IE CCP5IE CCP4IE CCP3IE --00 0000 --00 0000
IPR3
—
—
RC2IP
TX2IP
TMR4IP CCP5IP CCP4IP CCP3IP --11 1111 --11 1111
TRISB
PORTB Data Direction Register
1111 1111 1111 1111
TRISC
PORTC Data Direction Register
1111 1111 1111 1111
TRISCD PORTD Data Direction Register
1111 1111 1111 1111
TRISE
PORTE Data Direction Register
1111 1111 1111 1111
TRISF
PORTF Data Direction Register
1111 1111 1111 1111
TRISG
—
—
—
PORTG Data Direction Register
---1 1111 ---1 1111
TRISH
PORTH Data Direction Register
1111 1111 1111 1111
TMR1L
TMR1H
Timer1 Register Low Byte
Timer1 Register High Byte
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
T1CON
RD16
—
T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0-00 0000 u-uu uuuu
TMR2
Timer2 Register
0000 0000 0000 0000
T2CON
—
T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000
PR2
Timer2 Period Register
1111 1111 1111 1111
TMR3L
TMR3H
Timer3 Register Low Byte
Timer3 Register High Byte
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
T3CON
RD16
T3CCP2 T3CKPS1 T3CKPS0 T3CCP1 T3SYNC TMR3CS TMR3ON 0000 0000 uuuu uuuu
TMR4
Timer4 Register
0000 0000 0000 0000
T4CON
—
T4OUTPS3 T4OUTPS2 T4OUTPS1 T4OUTPS0 TMR4ON T4CKPS1 T4CKPS0 -000 0000 -000 0000
PR4
Timer4 Period Register
1111 1111 1111 1111
CCPR1L Enhanced Capture/Compare/PWM Register 1 Low Byte
xxxx xxxx uuuu uuuu
CCPR1H Enhanced Capture/Compare/PWM Register 1 High Byte
xxxx xxxx uuuu uuuu
CCP1CON P1M1
P1M0
DC1B1
DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 0000 0000 0000 0000
ECCP1AS ECCP1ASE ECCP1AS2 ECCP1AS1 ECCP1AS0 PSS1AC1 PSS1AC0 PSS1BD1 PSS1BD0 0000 0000 0000 0000
ECCP1DEL P1RSEN P1DC6
P1DC5
P1DC4
P1DC3 P1DC2 P1DC1 P1DC0 0000 0000 uuuu uuuu
CCPR2L Enhanced Capture/Compare/PWM Register 2 Low Byte
xxxx xxxx uuuu uuuu
CCPR2H Enhanced Capture/Compare/PWM Register 2 High Byte
xxxx xxxx uuuu uuuu
CCP2CON P2M1
P2M0
DC2B1
DC2B0 CCP2M3 CCP2M2 CCP2M1 CCP2M0 0000 0000 0000 0000
ECCP2AS ECCP2ASE ECCP2AS2 ECCP2AS1 ECCP2AS0 PSS2AC1 PSS2AC0 PSS2BD1 PSS2BD0 0000 0000 0000 0000
ECCP2DEL P2RSEN P2DC6
P2DC5
P2DC4
P2DC3 P2DC2 P2DC1 P2DC0 0000 0000 uuuu uuuu
CCPR3L Enhanced Capture/Compare/PWM Register 3 Low Byte
xxxx xxxx uuuu uuuu
CCPR3H Enhanced Capture/Compare/PWM Register 3 High Byte
xxxx xxxx uuuu uuuu
CCP3CON P3M1
P3M0
DC3B1
DC3B0 CCP3M3 CCP3M2 CCP3M1 CCP3M0 0000 0000 0000 0000
ECCP3AS ECCP3ASE ECCP3AS2 ECCP3AS1 ECCP3AS0 PSS3AC1 PSS3AC0 PSS3BD1 PSS3BD0 0000 0000 0000 0000
ECCP3DEL Px3RSEN P3DC6
P3DC5
P3DC4
P3DC3 P3DC2 P3DC1 P3DC0 0000 0000 uuuu uuuu
Legend: x = unknown, u = unchanged, — = unimplemented, read as ‘0’. Shaded cells are not used during ECCP operation.
Note 1: Enabled only in Microcontroller mode for PIC18F8525/8621 devices.
DS39612C-page 172
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