PIC18F6525_13 Datasheet, PDF (13/400 Pages) Microchip Technology – 64/80-Pin High-Performance, 64-Kbyte Enhanced Flash Microcontrollers with A/D

PIC18F6525/6621/8525/8621
TABLE 1-2: PIC18F6525/6621/8525/8621 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name
Pin Number
PIC18F6X2X PIC18F8X2X
Pin
Type
Buffer
Type
Description
PORTB is a bidirectional I/O port. PORTB
can be software programmed for internal
weak pull-ups on all inputs.
RB0/INT0/FLT0
RB0
INT0
FLT0
48
58
I/O
TTL
Digital I/O.
I
ST
External interrupt 0.
I
ST
PWM Fault input for ECCP1.
RB1/INT1
RB1
INT1
47
57
I/O
TTL
Digital I/O.
I
ST
External interrupt 1.
RB2/INT2
RB2
INT2
46
56
I/O
TTL
Digital I/O.
I
ST
External interrupt 2.
RB3/INT3/ECCP2/P2A
45
RB3
INT3
ECCP2⁽¹⁾
P2A⁽¹⁾
55
I/O
TTL
Digital I/O.
I/O
ST
External interrupt 3.
I/O
ST
Enhanced Capture 2 input, Compare 2
output, PWM2 output.
O
—
ECCP2 output P2A.
RB4/KBI0
RB4
KBI0
44
54
I/O
TTL
Digital I/O.
I
ST
Interrupt-on-change pin.
RB5/KBI1/PGM
RB5
KBI1
PGM
43
53
I/O
TTL
Digital I/O.
I
ST
Interrupt-on-change pin.
I/O
ST
Low-Voltage ICSP™ programming
enable pin.
RB6/KBI2/PGC
RB6
KBI2
PGC
42
52
I/O
TTL
Digital I/O.
I
ST
Interrupt-on-change pin.
I/O
ST
In-Circuit Debugger and
ICSP programming clock.
RB7/KBI3/PGD
RB7
KBI3
PGD
37
47
I/O
TTL
Digital I/O.
I
ST
Interrupt-on-change pin.
I/O
ST
In-Circuit Debugger and
ICSP programming data.
Legend: TTL = TTL compatible input
CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels
Analog = Analog input
I = Input
O
= Output
P = Power
OD = Open-Drain (no P diode to VDD)
Note 1: Alternate assignment for ECCP2/P2A in PIC18F8525/8621 devices when CCP2MX (CONFIG3H<0>) is not set (all
Program Memory modes except Microcontroller).
2: Default assignment for ECCP2/P2A when CCP2MX is set (all devices).
3: External memory interface functions are only available on PIC18F8525/8621 devices.
4: Default assignment for P1B/P1C/P3B/P3C for PIC18F8525/8621 devices when ECCPMX (CONFIG3H<1>) is set and for
all PIC18F6525/6621 devices.
5: Alternate assignment for ECCP2/P2A in PIC18F8525/8621 devices when CCP2MX is not set (Microcontroller mode).
6: PORTH and PORTJ (and their multiplexed functions) are only available on PIC18F8525/8621 devices.
7: Alternate assignment for P1B/P1C/P3B/P3C for PIC18F8525/8621 devices when ECCPMX (CONFIG3H<1>) is not set.
8: AVDD must be connected to a positive supply and AVSS must be connected to a ground reference for proper operation of
the part in user or ICSP™ modes. See parameter D001 for details.
9: RG5 is multiplexed with MCLR and is only available when the MCLR Resets are disabled.
 2003-2013 Microchip Technology Inc.
DS39612C-page 13