PIC18F6525_13 Datasheet, PDF (289/400 Pages) Microchip Technology – 64/80-Pin High-Performance, 64-Kbyte Enhanced Flash Microcontrollers with A/D

PIC18F6525/6621/8525/8621
BTG
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Q Cycle Activity:
Q1
Decode
Bit Toggle f
[ label ] BTG f,b[,a]
0  f  255
0b<7
a [0,1]
(f<b>)  f<b>
None
0111 bbba ffff ffff
Bit ‘b’ in data memory location ‘f’ is
inverted. If ‘a’ is ‘0’, the Access Bank will
be selected, overriding the BSR value. If
‘a’ = 1, then the bank will be selected as
per the BSR value (default).
1
1
Q2
Read
register ‘f’
Q3
Process
Data
Q4
Write
register ‘f’
Example:
BTG
PORTC, 4, 0
Before Instruction:
PORTC =
After Instruction:
PORTC =
0111 0101 [0x75]
0110 0101 [0x65]
BOV
Branch if Overflow
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Q Cycle Activity:
If Jump:
Q1
Decode
No
operation
If No Jump:
Q1
Decode
[ label ] BOV n
-128  n  127
if Overflow bit is ‘1’
(PC) + 2 + 2n  PC
None
1110 0100 nnnn nnnn
If the Overflow bit is ‘1’, then the
program will branch.
The 2’s complement number ‘2n’ is
added to the PC. Since the PC will have
incremented to fetch the next
instruction, the new address will be
PC + 2 + 2n. This instruction is then a
two-cycle instruction.
1
1(2)
Q2
Read literal
‘n’
No
operation
Q3
Process
Data
No
operation
Q4
Write to PC
No
operation
Q2
Read literal
‘n’
Q3
Process
Data
Q4
No
operation
Example:
HERE
Before Instruction
PC
=
After Instruction
If Overflow =
PC
=
If Overflow =
PC
=
BOV Jump
address (HERE)
1;
address (Jump)
0;
address (HERE + 2)
 2003-2013 Microchip Technology Inc.
DS39612C-page 289