PIC18F6525_13 Datasheet, PDF (136/400 Pages) Microchip Technology – 64/80-Pin High-Performance, 64-Kbyte Enhanced Flash Microcontrollers with A/D

PIC18F6525/6621/8525/8621
12.1 Timer1 Operation
Timer1 can operate in one of these modes:
• As a timer
• As a synchronous counter
• As an asynchronous counter
The operating mode is determined by the clock select
bit, TMR1CS (T1CON<1>).
When TMR1CS = 0, Timer1 increments every instruc-
tion cycle. When TMR1CS = 1, Timer1 increments on
every rising edge of the external clock input or the
Timer1 oscillator, if enabled.
When the Timer1 oscillator is enabled (T1OSCEN is
set), the RC1/T1OSI and RC0/T1OSO/T13CKI pins
become inputs. That is, the TRISC<1:0> value is
ignored and the pins are read as ‘0’.
Timer1 also has an internal “Reset input”. This Reset
can be generated by the ECCP1 or ECCP2 special
event trigger. This is discussed in detail in Section 12.4
“Resetting Timer1 Using an ECCP Special Trigger
Output”.
FIGURE 12-1:
TIMER1 BLOCK DIAGRAM
TMR1IF
Overflow
Interrupt
Flag Bit
T1OSO/T13CKI
T1OSI
ECCP Special Event Trigger
TMR1
CLR
TMR1H TMR1L
T1OSC
T1OSCEN
Enable
Oscillator⁽¹⁾
Synchronized
0
Clock Input
TMR1ON
On/Off
1
T1SYNC
FOSC/4
Internal
Clock
1
Prescaler
1, 2, 4, 8
0
2
T1CKPS1:T1CKPS0
TMR1CS
Synchronize
det
Sleep Input
Note 1: When enable bit T1OSCEN is cleared, the inverter and feedback resistor are turned off. This eliminates power drain.
FIGURE 12-2:
TIMER1 BLOCK DIAGRAM: 16-BIT READ/WRITE MODE
Data Bus<7:0>
8
TMR1H
8
8
Write TMR1L
Read TMR1L
ECCP Special Event Trigger
TMR1IF
Overflow
Interrupt
Flag bit
T1OSO/T13CKI
T1OSI
8
TMR1
Timer 1
High Byte
CLR
TMR1L
T1OSC
T1OSCEN
Enable
Oscillator⁽¹⁾
Synchronized
0
Clock Input
TMR1ON
On/Off
1
T1SYNC
1
FOSC/4
Internal 0
Clock
TMR1CS
Prescaler
1, 2, 4, 8
2
T1CKPS1:T1CKPS0
Synchronize
det
Sleep Input
Note 1: When enable bit T1OSCEN is cleared, the inverter and feedback resistor are turned off. This eliminates power drain.
DS39612C-page 136
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