PIC18F6525_13 Datasheet, PDF (285/400 Pages) Microchip Technology – 64/80-Pin High-Performance, 64-Kbyte Enhanced Flash Microcontrollers with A/D

PIC18F6525/6621/8525/8621
BNC
Branch if Not Carry
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Q Cycle Activity:
If Jump:
Q1
Decode
No
operation
If No Jump:
Q1
Decode
[ label ] BNC n
-128  n  127
if Carry bit is ‘0’
(PC) + 2 + 2n  PC
None
1110 0011 nnnn nnnn
If the Carry bit is ‘0’, then the program
will branch.
The 2’s complement number ‘2n’ is
added to the PC. Since the PC will have
incremented to fetch the next
instruction, the new address will be
PC + 2 + 2n. This instruction is then a
two-cycle instruction.
1
1(2)
Q2
Read literal
‘n’
No
operation
Q3
Process
Data
No
operation
Q4
Write to PC
No
operation
Q2
Read literal
‘n’
Q3
Process
Data
Q4
No
operation
Example:
HERE
BNC Jump
Before Instruction
PC
After Instruction
If Carry =
PC =
If Carry =
PC =
= address (HERE)
0;
address (Jump)
1;
address (HERE + 2)
BNN
Branch if Not Negative
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Q Cycle Activity:
If Jump:
Q1
Decode
No
operation
If No Jump:
Q1
Decode
[ label ] BNN n
-128  n  127
if Negative bit is ‘0’
(PC) + 2 + 2n  PC
None
1110 0111 nnnn nnnn
If the Negative bit is ‘0’, then the
program will branch.
The 2’s complement number ‘2n’ is
added to the PC. Since the PC will have
incremented to fetch the next
instruction, the new address will be
PC + 2 + 2n. This instruction is then a
two-cycle instruction.
1
1(2)
Q2
Read literal
‘n’
No
operation
Q3
Process
Data
No
operation
Q4
Write to PC
No
operation
Q2
Read literal
‘n’
Q3
Process
Data
Q4
No
operation
Example:
HERE
Before Instruction
PC
=
After Instruction
If Negative =
PC
=
If Negative =
PC
=
BNN Jump
address (HERE)
0;
address (Jump)
1;
address (HERE + 2)
 2003-2013 Microchip Technology Inc.
DS39612C-page 285