PIC18F6525_13 Datasheet, PDF (349/400 Pages) Microchip Technology – 64/80-Pin High-Performance, 64-Kbyte Enhanced Flash Microcontrollers with A/D

PIC18F6525/6621/8525/8621
TABLE 27-17: EXAMPLE SPI™ MODE REQUIREMENTS (SLAVE MODE TIMING, CKE = 0)
Param.
No.
Symbol
Characteristic
Min
Max Units Conditions
70
TssL2scH, SS  to SCK  or SCK  Input
TssL2scL
TCY
—
71
TscH
71A
SCK Input High Time
(Slave mode)
Continuous
Single Byte
1.25 TCY + 30 —
40
—
72
TscL
72A
SCK Input Low Time
(Slave mode)
Continuous
Single Byte
1.25 TCY + 30 —
40
—
73
TdiV2scH, Setup Time of SDI Data Input to SCK Edge
TdiV2scL
100
—
73A
TB2B
Last Clock Edge of Byte 1 to the First Clock Edge of Byte 2 1.5 TCY + 40 —
74
TscH2diL, Hold Time of SDI Data Input to SCK Edge
TscL2diL
100
—
75
TdoR
SDO Data Output Rise Time
PIC18F6525/6621/
—
25
8525/8621
PIC18F6525/6621/
45
8525/8621
76
TdoF
SDO Data Output Fall Time
—
25
77
TssH2doZ SS  to SDO Output High-impedance
10
50
78
TscR
SCK Output Rise Time (Master mode) PIC18F6525/6621/
—
25
8525/8621
PIC18F6525/6621/
45
8525/8621
79
TscF
SCK Output Fall Time (Master mode)
—
25
80
TscH2doV, SDO Data Output Valid after SCK
PIC18F6525/6621/
—
50
TscL2doV Edge
8525/8621
PIC18F6525/6621/
100
8525/8621
83
TscH2ssH, SS  after SCK Edge
TscL2ssH
1.5 TCY + 40 —
Note 1: Requires the use of Parameter #73A.
2: Only if Parameter #71A and #72A are used.
ns
ns
ns (Note 1)
ns
ns (Note 1)
ns
ns (Note 2)
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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DS39612C-page 349