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PIC18F6525_13 Datasheet, PDF (293/400 Pages) Microchip Technology – 64/80-Pin High-Performance, 64-Kbyte Enhanced Flash Microcontrollers with A/D | |||
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PIC18F6525/6621/8525/8621
CPFSGT
Compare f with W, Skip if f > W
Syntax:
[ label ] CPFSGT f [,a]
Operands:
0 ï£ f ï£ 255
a ï [0,1]
Operation:
(f) ïï ï¨W);
skip if (f) > (W)
(unsigned comparison)
Status Affected:
None
Encoding:
0110 010a ffff ffff
Description:
Compares the contents of data memory
location âfâ to the contents of the W by
performing an unsigned subtraction.
If the contents of âfâ are greater than the
contents of WREG, then the fetched
instruction is discarded and a NOP is
executed instead, making this a
two-cycle instruction. If âaâ is â0â, the
Access Bank will be selected,
overriding the BSR value. If âaâ = 1, then
the bank will be selected as per the
BSR value (default).
Words:
1
Cycles:
1(2)
Note: 3 cycles if skip and followed
by a 2-word instruction.
Q Cycle Activity:
Q1
Q2
Q3
Decode
Read
register âfâ
Process
Data
If skip:
Q1
Q2
Q3
No
operation
No
operation
No
operation
If skip and followed by 2-word instruction:
Q1
Q2
Q3
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
Q4
No
operation
Q4
No
operation
Q4
No
operation
No
operation
Example:
HERE
CPFSGT REG, 0
NGREATER :
GREATER :
Before Instruction
PC
=
W
=
After Instruction
If REG ï¾
PC =
If REG ï£
PC =
Address (HERE)
?
W;
Address (GREATER)
W;
Address (NGREATER)
CPFSLT
Compare f with W, Skip if f < W
Syntax:
[ label ] CPFSLT f [,a]
Operands:
0 ï£ f ï£ 255
a ï [0,1]
Operation:
(f) âï ï¨W);
skip if (f) < (W)
(unsigned comparison)
Status Affected:
None
Encoding:
0110 000a ffff ffff
Description:
Compares the contents of data memory
location âfâ to the contents of W by
performing an unsigned subtraction.
If the contents of âfâ are less than the
contents of W, then the fetched
instruction is discarded and a NOP is
executed instead, making this a
two-cycle instruction. If âaâ is â0â, the
Access Bank will be selected. If âaâ is â1â,
the BSR will not be overridden (default).
Words:
1
Cycles:
1(2)
Note: 3 cycles if skip and followed
by a 2-word instruction.
Q Cycle Activity:
Q1
Q2
Q3
Decode
Read
register âfâ
Process
Data
If skip:
Q1
Q2
Q3
No
operation
No
operation
No
operation
If skip and followed by 2-word instruction:
Q1
Q2
Q3
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
Q4
No
operation
Q4
No
operation
Q4
No
operation
No
operation
Example:
HERE
NLESS
LESS
CPFSLT REG, 1
:
:
Before Instruction
PC
=
W
=
After Instruction
If REG <
PC =
If REG ï³
PC =
Address (HERE)
?
W;
Address (LESS)
W;
Address (NLESS)
ï£ 2003-2013 Microchip Technology Inc.
DS39612C-page 293
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