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PIC18F6525_13 Datasheet, PDF (286/400 Pages) Microchip Technology – 64/80-Pin High-Performance, 64-Kbyte Enhanced Flash Microcontrollers with A/D | |||
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PIC18F6525/6621/8525/8621
BNOV
Branch if Not Overflow
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Q Cycle Activity:
If Jump:
Q1
Decode
No
operation
If No Jump:
Q1
Decode
[ label ] BNOV n
-128 ï£ n ï£ 127
if Overflow bit is â0â
(PC) + 2 + 2n ï® PC
None
1110 0101 nnnn nnnn
If the Overflow bit is â0â, then the
program will branch.
The 2âs complement number â2nâ is
added to the PC. Since the PC will have
incremented to fetch the next
instruction, the new address will be
PC + 2 + 2n. This instruction is then a
two-cycle instruction.
1
1(2)
Q2
Read literal
ânâ
No
operation
Q3
Process
Data
No
operation
Q4
Write to PC
No
operation
Q2
Read literal
ânâ
Q3
Process
Data
Q4
No
operation
Example:
HERE
Before Instruction
PC
=
After Instruction
If Overflow =
PC
=
If Overflow =
PC
=
BNOV Jump
address (HERE)
0;
address (Jump)
1;
address (HERE + 2)
BNZ
Branch if Not Zero
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Q Cycle Activity:
If Jump:
Q1
Decode
No
operation
If No Jump:
Q1
Decode
[ label ] BNZ n
-128 ï£ n ï£ 127
if Zero bit is â0â
(PC) + 2 + 2n ï® PC
None
1110 0001 nnnn nnnn
If the Zero bit is â0â, then the
program will branch.
The 2âs complement number â2nâ is
added to the PC. Since the PC will have
incremented to fetch the next
instruction, the new address will be
PC + 2 + 2n. This instruction is then a
two-cycle instruction.
1
1(2)
Q2
Read literal
ânâ
No
operation
Q3
Process
Data
No
operation
Q4
Write to PC
No
operation
Q2
Read literal
ânâ
Q3
Process
Data
Q4
No
operation
Example:
HERE
BNZ Jump
Before Instruction
PC
After Instruction
If Zero =
PC =
If Zero =
PC =
= address (HERE)
0;
address (Jump)
1;
address (HERE + 2)
DS39612C-page 286
ï£ 2003-2013 Microchip Technology Inc.
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