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| PIC18F6525_13 Datasheet, PDF (270/400 Pages) Microchip Technology – 64/80-Pin High-Performance, 64-Kbyte Enhanced Flash Microcontrollers with A/D | |||
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PIC18F6525/6621/8525/8621
FIGURE 24-2:
WAKE-UP FROM SLEEP THROUGH INTERRUPT(1,2)
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1
OSC1
CLKO(4)
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
TOST(2)
INT pin
INTF Flag
(INTCON<1>)
Interrupt Latency(3)
GIEH bit
(INTCON<7>)
INSTRUCTION FLOW
PC
PC
Instruction
Fetched
Inst(PC) = Sleep
Instruction
Executed
Inst(PC â 1)
Processor in
Sleep
PC + 2
Inst(PC + 2)
Sleep
PC + 4
PC + 4
Inst(PC + 4)
Inst(PC + 2)
PC + 4
Dummy Cycle
0008h
Inst(0008h)
Dummy Cycle
000Ah
Inst(000Ah)
Inst(0008h)
Note 1:
2:
3:
4:
XT, HS or LP Oscillator mode assumed.
GIE = 1 assumed. In this case, after wake-up, the processor jumps to the interrupt routine. If GIE = 0, execution will continue in-line.
TOST = 1024 TOSC (drawing not to scale). This delay will not occur for RC and EC Oscillator modes.
CLKO is not available in these oscillator modes but shown here for timing reference.
24.4 Program Verification and
Code Protection
The overall structure of the code protection on the
PIC18 Flash devices differs significantly from other PIC
devices.
The user program memory is divided on binary bound-
aries into four blocks of 16 Kbytes each. The first block is
further divided into a boot block of 2048 bytes and a
second block (Block 0) of 14 Kbytes.
Each of the blocks has three code protection bits
associated with them. They are:
⢠Code-Protect bit (CPn)
⢠Write-Protect bit (WRTn)
⢠External Block Table Read bit (EBTRn)
Figure 24-3 shows the program memory organization
for 48 and 64-Kbyte devices and the specific code
protection bit associated with each block. The actual
locations of the bits are summarized in Table 24-3.
FIGURE 24-3:
CODE-PROTECTED PROGRAM MEMORY FOR PIC18F6525/6621/8525/8621
DEVICES
MEMORY SIZE/DEVICE
48 Kbytes
(PIC18FX525)
64 Kbytes
(PIC18FX621)
Boot Block
Boot Block
Block 0
Block 0
Block 1
Block 1
Block 2
Block 2
Unimplemented, read â0â
Block 3
Address
Range
000000h
0007FFh
000800h
003FFFh
004000h
007FFFh
008000h
00BFFFh
00C000h
00FFFFh
Block Code Protection
Controlled By:
CPB, WRTB, EBTRB
CP0, WRT0, EBTR0
CP1, WRT1, EBTR1
CP2, WRT2, EBTR2
CP3, WRT3, EBTR3
DS39612C-page 270
ï£ 2003-2013 Microchip Technology Inc.
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