PIC18F6525_13 Datasheet, PDF(241/400 Page) Microchip Technology – 64/80-Pin High-Performance, 64-Kbyte Enhanced Flash Microcontrollers with A/D

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PIC18F6525_13 Datasheet, PDF (241/400 Pages) Microchip Technology – 64/80-Pin High-Performance, 64-Kbyte Enhanced Flash Microcontrollers with A/D

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PIC18F6525/6621/8525/8621

20.6 Use of the ECCP2 Trigger

An A/D conversion can be started by the special event

trigger of the ECCP2 module. This requires that the

CCP2M3:CCP2M0 bits (CCP2CON<3:0>) be pro-

grammed as â1011â and that the A/D module is enabled

(ADON bit is set). When the trigger occurs, the GO/

DONE bit will be set, starting the A/D conversion and

the Timer1 (or Timer3) counter will be reset to zero.

Timer1 (or Timer3) is reset to automatically repeat the

A/D acquisition period with minimal software overhead

(moving ADRESH/ADRESL to the desired location).

The appropriate analog input channel must be selected

and the minimum acquisition done before the special

event trigger sets the GO/DONE bit and starts a

conversion.

If the A/D module is not enabled (ADON is cleared), the

special event trigger will be ignored by the A/D module

but will still reset the Timer1 (or Timer3) counter.

TABLE 20-2: SUMMARY OF REGISTERS ASSOCIATED WITH A/D

Name

Bit 7

Bit 6

Bit 5

Bit 4 Bit 3

Bit 2

Bit 1

Bit 0

Value on

POR, BOR

Value on

all other

Resets

INTCON

PIR1

PIE1

IPR1

GIE/

GIEH

PSPIF(1)

PSPIE(1)

PSPIP(1)

PEIE/

GIEL

ADIF

ADIE

ADIP

TMR0IE INT0IE RBIE TMR0IF INT0IF

RBIF 0000 000x 0000 000u

RC1IF

RC1IE

RC1IP

TX1IF

TX1IE

TX1IP

SSPIF

SSPIE

SSPIP

CCP1IF

CCP1IE

CCP1IP

TMR2IF

TMR2IE

TMR2IP

TMR1IF

TMR1IE

TMR1IP

0000 0000

0000 0000

1111 1111

0000 0000

0000 0000

1111 1111

PIR2

â

CMIF

â

EEIF BCLIF LVDIF TMR3IF CCP2IF -0-0 0000 -0-0 0000

PIE2

â

CMIE

â

EEIE BCLIE LVDIE TMR3IE CCP2IE -0-0 0000 -0-0 0000

IPR2

â

CMIP

â

EEIP BCLIP LVDIP TMR3IP CCP2IP -1-1 1111 -1-1 1111

ADRESH A/D Result Register High Byte

xxxx xxxx uuuu uuuu

ADRESL A/D Result Register Low Byte

xxxx xxxx uuuu uuuu

ADCON0

â

â

CHS3 CHS3 CHS1 CHS0 GO/DONE ADON --00 0000 --00 0000

ADCON1

â

â

VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0 --00 0000 --00 0000

ADCON2

PORTA

TRISA

ADFM

â

â

â

ACQT2 ACQT1 ACQT0 ADCS2

RA6(2)

RA5

RA4

RA3

RA2

TRISA6(2) PORTA Data Direction Register

ADCS1

RA1

ADCS0

RA0

0-00 0000

-x0x 0000

-111 1111

0-00 0000

-u0u 0000

-111 1111

PORTF

RF7

RF6

RF5

RF4

RF3

RF2

RF1

RF0 x000 0000 u000 0000

TRISF PORTF Data Direction Control Register

PORTH(3) RH7

RH6

RH5

RH4

TRISH(3) PORTH Data Direction Control Register

RH3

RH2

RH1

RH0

1111 1111

0000 xxxx

1111 1111

1111 1111

0000 uuuu

1111 1111

Legend:

Note 1:

2:

3:

x = unknown, u = unchanged, â = unimplemented, read as â0â. Shaded cells are not used for A/D conversion.

Enabled only in Microcontroller mode for PIC18F8525/8621 devices.

RA6 and associated bits are configured as port pins in RCIO and ECIO Oscillator modes only and read â0â in all other

oscillator modes.

Implemented on PIC18F8525/8621 devices only, otherwise read as â0â.

ï£ 2003-2013 Microchip Technology Inc.

DS39612C-page 241

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