PIC18F6525_13 Datasheet, PDF (271/400 Pages) Microchip Technology – 64/80-Pin High-Performance, 64-Kbyte Enhanced Flash Microcontrollers with A/D

PIC18F6525/6621/8525/8621
TABLE 24-3: SUMMARY OF REGISTERS ASSOCIATED WITH CODE PROTECTION
File Name
Bit 7
Bit 6
Bit 5
300008h CONFIG5L
—
—
—
300009h CONFIG5H CPD
CPB
—
30000Ah CONFIG6L
—
—
—
30000Bh CONFIG6H WRTD WRTB WRTC
30000Ch CONFIG7L
—
—
—
30000Dh CONFIG7H —
EBTRB
—
Legend: Shaded cells are unimplemented.
Note 1: Unimplemented in PIC18FX525 devices.
Bit 4
—
—
—
—
—
—
Bit 3
CP3⁽¹⁾
—
WRT3⁽¹⁾
—
EBTR3⁽¹⁾
—
Bit 2
CP2
—
WRT2
—
EBTR2
—
Bit 1
CP1
—
WRT1
—
EBTR1
—
Bit 0
CP0
—
WRT0
—
EBTR0
—
24.4.1 PROGRAM MEMORY
CODE PROTECTION
The user memory may be read to or written from any
location using the table read and table write instruc-
tions. The Device ID register may be read with table
reads. The Configuration registers may be read and
written with the table read and table write instructions.
In user mode, the CPn bits have no direct effect. CPn
bits inhibit external reads and writes. A block of user
memory may be protected from table writes if the
WRTn configuration bit is ‘0’. The EBTRn bits control
table reads. For a block of user memory with the
EBTRn bit set to ‘0’, a table read instruction that
executes from within that block is allowed to read. A
table read instruction that executes from a location out-
side of that block is not allowed to read and will result
in reading ‘0’s. Figures 24-4 through 24-6 illustrate
table write and table read protection.
Note:
Code protection bits may only be written to
a ‘0’ from a ‘1’ state. It is not possible to
write a ‘1’ to a bit in the ‘0’ state. Code
protection bits are only set to ‘1’ by a full
chip erase or block erase function. The full
chip erase and block erase functions can
only be initiated via ICSP or an external
programmer.
 2003-2013 Microchip Technology Inc.
DS39612C-page 271