PIC18F6525_13 Datasheet, PDF (16/400 Pages) Microchip Technology – 64/80-Pin High-Performance, 64-Kbyte Enhanced Flash Microcontrollers with A/D

PIC18F6525/6621/8525/8621
TABLE 1-2: PIC18F6525/6621/8525/8621 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name
Pin Number
PIC18F6X2X PIC18F8X2X
Pin
Type
Buffer
Type
Description
PORTE is a bidirectional I/O port.
RE0/AD8/RD/P2D
2
RE0
AD8⁽³⁾
RD
P2D
4
I/O
ST
Digital I/O.
I/O
TTL
External memory address/data 8.
I
TTL
Read control for Parallel Slave Port.
O
—
ECCP2 output P2D.
RE1/AD9/WR/P2C
1
RE1
AD9⁽³⁾
WR
P2C
3
I/O
ST
Digital I/O.
I/O
TTL
External memory address/data 9.
I
TTL
Write control for Parallel Slave Port.
O
ST
ECCP2 output P2C.
RE2/AD10/CS/P2B
64
RE2
AD10⁽³⁾
CS
P2B
78
I/O
ST
Digital I/O.
I/O
TTL
External memory address/data 10.
I
TTL
Chip select control for Parallel Slave Port.
O
—
ECCP2 output P2B.
RE3/AD11/P3C
RE3
AD11⁽³⁾
P3C⁽⁴⁾
63
77
I/O
ST
Digital I/O.
I/O
TTL
External memory address/data 11.
O
—
ECCP3 output P3C.
RE4/AD12/P3B
RE4
AD12⁽³⁾
P3B⁽⁴⁾
62
76
I/O
ST
Digital I/O.
I/O
TTL
External memory address/data 12.
O
—
ECCP3 output P3B.
RE5/AD13/P1C
RE5
AD13⁽³⁾
P1C⁽⁴⁾
61
75
I/O
ST
Digital I/O.
I/O
TTL
External memory address/data 13.
O
—
ECCP1 output P1C.
RE6/AD14/P1B
RE6
AD14⁽³⁾
P1B⁽⁴⁾
60
74
I/O
ST
Digital I/O.
I/O
TTL
External memory address/data 14.
O
—
ECCP1 output P1B.
RE7/AD15/ECCP2/P2A
59
RE7
AD15⁽³⁾
ECCP2⁽⁵⁾
P2A⁽⁵⁾
73
I/O
ST
Digital I/O.
I/O
TTL
External memory address/data 15.
I/O
ST
Enhanced Capture 2 input, Compare 2
output, PWM 2 output.
O
—
ECCP2 output P2A.
Legend: TTL = TTL compatible input
CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels
Analog = Analog input
I = Input
O
= Output
P = Power
OD = Open-Drain (no P diode to VDD)
Note 1: Alternate assignment for ECCP2/P2A in PIC18F8525/8621 devices when CCP2MX (CONFIG3H<0>) is not set (all
Program Memory modes except Microcontroller).
2: Default assignment for ECCP2/P2A when CCP2MX is set (all devices).
3: External memory interface functions are only available on PIC18F8525/8621 devices.
4: Default assignment for P1B/P1C/P3B/P3C for PIC18F8525/8621 devices when ECCPMX (CONFIG3H<1>) is set and for
all PIC18F6525/6621 devices.
5: Alternate assignment for ECCP2/P2A in PIC18F8525/8621 devices when CCP2MX is not set (Microcontroller mode).
6: PORTH and PORTJ (and their multiplexed functions) are only available on PIC18F8525/8621 devices.
7: Alternate assignment for P1B/P1C/P3B/P3C for PIC18F8525/8621 devices when ECCPMX (CONFIG3H<1>) is not set.
8: AVDD must be connected to a positive supply and AVSS must be connected to a ground reference for proper operation of
the part in user or ICSP™ modes. See parameter D001 for details.
9: RG5 is multiplexed with MCLR and is only available when the MCLR Resets are disabled.
DS39612C-page 16
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