PIC18F6525_13 Datasheet, PDF(231/400 Page) Microchip Technology – 64/80-Pin High-Performance, 64-Kbyte Enhanced Flash Microcontrollers with A/D

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PIC18F6525_13 Datasheet, PDF (231/400 Pages) Microchip Technology – 64/80-Pin High-Performance, 64-Kbyte Enhanced Flash Microcontrollers with A/D

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PIC18F6525/6621/8525/8621

19.4 EUSART Synchronous Slave

Mode

Synchronous Slave mode is entered by clearing bit

CSRC (TXSTAx<7>). This mode differs from the Syn-

chronous Master mode in that the shift clock is supplied

externally at the CKx pin (instead of being supplied

internally in Master mode). This allows the device to

transfer or receive data while in any low-power mode.

19.4.1 EUSART SYNCHRONOUS SLAVE

TRANSMIT

The operation of the Synchronous Master and Slave

modes are identical except in the case of the Sleep

mode.

If two words are written to the TXREGx and then the

SLEEP instruction is executed, the following will occur:

a) The first word will immediately transfer to the

TSR register and transmit.

b) The second word will remain in the TXREGx

register.

c) Flag bit TXxIF will not be set.

d) When the first word has been shifted out of TSR,

the TXREGx register will transfer the second

word to the TSR and flag bit TXxIF will now be

set.

e) If enable bit TXxIE is set, the interrupt will wake

the chip from Sleep. If the global interrupt is

enabled, the program will branch to the interrupt

vector.

To set up a Synchronous Slave Transmission:

1. Enable the synchronous slave serial port by

setting bits SYNC and SPEN and clearing bit

CSRC.

2. Clear bits CREN and SREN.

3. If interrupts are desired, set enable bit TXxIE.

4. If 9-bit transmission is desired, set bit TX9.

5. Enable the transmission by setting enable bit

TXEN.

6. If 9-bit transmission is selected, the ninth bit

should be loaded in bit TX9D.

7. Start transmission by loading data to the

TXREGx register.

8. If using interrupts, ensure that the GIE and PEIE

bits in the INTCON register (INTCON<7:6>) are

set.

TABLE 19-9: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE TRANSMISSION

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Value on

POR, BOR

Value on

all other

Resets

INTCON

PIR1

PIE1

IPR1

GIE/GIEH

PSPIF(1)

PSPIE(1)

PSPIP(1)

PEIE/GIEL

ADIF

ADIE

ADIP

TMR0IE

RC1IF

RC1IE

RC1IP

INT0IE

TX1IF

TX1IE

TX1IP

RBIE

SSPIF

SSPIE

SSPIP

TMR0IF

CCP1IF

CCP1IE

CCP1IP

INT0IF

TMR2IF

TMR2IE

TMR2IP

RBIF

TMR1IF

TMR1IE

TMR1IP

0000 000x

0000 0000

0000 0000

1111 1111

0000 000u

0000 0000

0000 0000

1111 1111

PIR3

â

â

RC2IF TX2IF TMR4IF CCP5IF CCP4IF CCP3IF --00 0000 --00 0000

PIE3

â

â

RC2IE TX2IE TMR4IE CCP5IE CCP4IE CCP3IE --00 0000 --00 0000

IPR3

â

â

RC2IP TX2IP TMR4IP CCP5IP CCP4IP CCP3IP --11 1111 --11 1111

RCSTAx

SPEN

RX9

SREN CREN ADDEN FERR OERR RX9D 0000 000x 0000 000x

TXREGx Enhanced USARTx Transmit Register

0000 0000 0000 0000

TXSTAx

CSRC

TX9

TXEN SYNC SENDB BRGH TRMT TX9D 0000 0010 0000 0010

BAUDCONx

â

RCIDL

â

SCKP BRG16 â

WUE ABDEN -1-0 0-00 -1-0 0-00

SPBRGHx Enhanced USARTx Baud Rate Generator Register High Byte

0000 0000 0000 0000

SPBRGx Enhanced USARTx Baud Rate Generator Register Low Byte

0000 0000 0000 0000

Legend: x = unknown, â = unimplemented, read as â0â. Shaded cells are not used for synchronous slave transmission.

Note 1: Enabled only in Microcontroller mode for PIC18F8525/8621 devices.

ï£ 2003-2013 Microchip Technology Inc.

DS39612C-page 231

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