PIC18F6525_13 Datasheet, PDF(125/400 Page) Microchip Technology – 64/80-Pin High-Performance, 64-Kbyte Enhanced Flash Microcontrollers with A/D

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PIC18F6525_13 Datasheet, PDF (125/400 Pages) Microchip Technology – 64/80-Pin High-Performance, 64-Kbyte Enhanced Flash Microcontrollers with A/D

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PIC18F6525/6621/8525/8621

10.9 PORTJ, TRISJ and LATJ Registers

Note: PORTJ is available only on PIC18F8525/

8621 devices.

PORTJ is an 8-bit wide, bidirectional port. The corre-

sponding data direction register is TRISJ. Setting a

TRISJ bit (= 1) will make the corresponding PORTJ pin

an input (i.e., put the corresponding output driver in a

high-impedance mode). Clearing a TRISJ bit (= 0) will

make the corresponding PORTJ pin an output (i.e., put

the contents of the output latch on the selected pin).

The Data Latch register (LATJ) is also memory

mapped. Read-modify-write operations on the LATJ

register, read and write the latched output value for

PORTJ.

PORTJ is multiplexed with the system bus as the

external memory interface; I/O port functions are only

available when the system bus is disabled. When

operating as the external memory interface, PORTJ

provides the control signal to external memory devices.

The RJ5 pin is not multiplexed with any system bus

functions.

When enabling peripheral functions, care should be

taken in defining TRIS bits for each PORTJ pin. Some

peripherals override the TRIS bit to make a pin an

output, while other peripherals override the TRIS bit to

make a pin an input. The user should refer to the corre-

sponding peripheral section for the correct TRIS bit

settings.

Note: On a Power-on Reset, these pins are

configured as digital inputs.

The pin override value is not loaded into the TRIS reg-

ister. This allows read-modify-write of the TRIS register

without concern due to peripheral overrides.

EXAMPLE 10-9: INITIALIZING PORTJ

CLRF

CLRF

MOVLW

MOVWF

PORTJ

LATJ

0xCF

TRISJ

; Initialize PORTG by

; clearing output

; data latches

; Alternate method

; to clear output

; data latches

; Value used to

; initialize data

; direction

; Set RJ3:RJ0 as inputs

; RJ5:RJ4 as output

; RJ7:RJ6 as inputs

FIGURE 10-21:

PORTJ BLOCK DIAGRAM

IN I/O MODE

RD LATJ

Data

Bus

WR LATJ

or

PORTJ

WR TRISJ

RD TRISJ

D

Q

CK

Data Latch

DQ

CK

TRIS Latch

I/O pin(1)

Schmitt

Trigger

Input

Buffer

RD PORTJ

Q

D

ENEN

Note 1: I/O pins have diode protection to VDD and VSS.

ï£ 2003-2013 Microchip Technology Inc.

DS39612C-page 125

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