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| PIC18F6525_13 Datasheet, PDF (232/400 Pages) Microchip Technology – 64/80-Pin High-Performance, 64-Kbyte Enhanced Flash Microcontrollers with A/D | |||
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PIC18F6525/6621/8525/8621
19.4.2 EUSART SYNCHRONOUS SLAVE
RECEPTION
The operation of the Synchronous Master and Slave
modes is identical except in the case of Sleep or any
Idle mode and bit SREN, which is a âdonât careâ in
Slave mode.
If receive is enabled by setting the CREN bit prior to
entering Sleep or any Idle mode, then a word may be
received while in this Low-Power mode. Once the word
is received, the RSR register will transfer the data to the
RCREGx register; if the RC1IE enable bit is set, the
interrupt generated will wake the chip from Low-Power
mode. If the global interrupt is enabled, the program will
branch to the interrupt vector.
To set up a Synchronous Slave Reception:
1. Enable the synchronous master serial port by
setting bits SYNC and SPEN and clearing bit
CSRC.
2. If interrupts are desired, set enable bit RCxIE.
3. If 9-bit reception is desired, set bit RX9.
4. To enable reception, set enable bit CREN.
5. Flag bit RCxIF will be set when reception is com-
plete. An interrupt will be generated if enable bit
RCxIE was set.
6. Read the RCSTAx register to get the 9th bit (if
enabled) and determine if any error occurred
during reception.
7. Read the 8-bit received data by reading the
RCREGx register.
8. If any error occurred, clear the error by clearing
bit CREN.
9. If using interrupts, ensure that the GIE and PEIE
bits in the INTCON register (INTCON<7:6>) are
set.
TABLE 19-10: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE RECEPTION
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Value on
all other
Resets
INTCON
PIR1
PIE1
IPR1
GIE/GIEH
PSPIF(1)
PSPIE(1)
PSPIP(1)
PEIE/GIEL
ADIF
ADIE
ADIP
TMR0IE
RC1IF
RC1IE
RC1IP
INT0IE
TX1IF
TX1IE
TX1IP
RBIE
SSPIF
SSPIE
SSPIP
TMR0IF
CCP1IF
CCP1IE
CCP1IP
INT0IF RBIF
TMR2IF TMR1IF
TMR2IE TMR1IE
TMR2IP TMR1IP
0000 000x
0000 0000
0000 0000
1111 1111
0000 000u
0000 0000
0000 0000
1111 1111
PIR3
â
â
RC2IF TX2IF TMR4IF CCP5IF CCP4IF CCP3IF --00 0000 --00 0000
PIE3
â
â
RC2IE TX2IE TMR4IE CCP5IE CCP4IE CCP3IE --00 0000 --00 0000
IPR3
â
â
RC2IP TX2IP TMR4IP CCP5IP CCP4IP CCP3IP --11 1111 --11 1111
RCSTAx
SPEN
RX9
SREN CREN ADDEN FERR OERR RX9D 0000 000x 0000 000x
RCREGx Enhanced USARTx Receive Register
0000 0000 0000 0000
TXSTAx
CSRC
TX9
TXEN SYNC SENDB BRGH TRMT TX9D 0000 0010 0000 0010
BAUDCONx
â
RCIDL
â
SCKP BRG16 â
WUE ABDEN -1-0 0-00 -1-0 0-00
SPBRGHx Enhanced USARTx Baud Rate Generator Register High Byte
0000 0000 0000 0000
SPBRGx Enhanced USARTx Baud Rate Generator Register Low Byte
0000 0000 0000 0000
Legend: x = unknown, â = unimplemented, read as â0â. Shaded cells are not used for synchronous slave reception.
Note 1: Enabled only in Microcontroller mode for PIC18F8525/8621 devices.
DS39612C-page 232
ï£ 2003-2013 Microchip Technology Inc.
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