PIC18F6525_13 Datasheet, PDF (339/400 Pages) Microchip Technology – 64/80-Pin High-Performance, 64-Kbyte Enhanced Flash Microcontrollers with A/D

PIC18F6525/6621/8525/8621
TABLE 27-7: PLL CLOCK TIMING SPECIFICATIONS (VDD = 4.2 TO 5.5V)
Param. No. Sym
Characteristic
Min Typ† Max Units
Conditions
FOSC Oscillator Frequency Range
4
— 10 MHz HS mode
FSYS On-Chip VCO System Frequency
16
—
40 MHz HS mode
t_rc
CLK
PLL Start-up Time (Lock Time)
CLKO Stability (Jitter)
—
—
2
ms
-2
—
+2 %
† Data in “Typ” column is at 5V, 25C, unless otherwise stated. These parameters are for design guidance
only and are not tested.
FIGURE 27-6:
OSC1
CLKO AND I/O TIMING
Q4
Q1
10
Q2
Q3
11
CLKO
13
14
I/O pin
(input)
I/O pin
(output)
17
Old Value
Note:
20, 21
Refer to Figure 27-4 for load conditions.
19
18
15
New Value
12
16
TABLE 27-8: CLKO AND I/O TIMING REQUIREMENTS
Param
No.
Symbol
Characteristic
Min
Typ
Max
Units Conditions
10
TosH2ckL OSC1  to CLKO 
—
75
200
11
TosH2ckH OSC1  to CLKO 
—
75
200
12
TckR
CLKO Rise Time
—
35
100
13
TckF
CLKO Fall Time
—
35
100
14
TckL2ioV CLKO  to Port Out Valid
—
— 0.5 TCY + 20
15
TioV2ckH Port In Valid before CLKO 
0.25 TCY + 25 —
—
16
TckH2ioI Port In Hold after CLKO 
0
—
—
17
TosH2ioV OSC1  (Q1 cycle) to Port Out Valid
—
50
150
18
TosH2ioI OSC1  (Q2 cycle) to Port PIC18F6525/6621/
100
—
—
Input Invalid (I/O in hold time) 8525/8621
18A
PIC18LF6X2X/8X2X
200
—
—
19
TioV2osH Port Input Valid to OSC1 (I/O in setup time)
0
—
—
20
TioR
Port Output Rise Time
PIC18F6525/6621/
—
10
25
8525/8621
20A
PIC18LF6X2X/8X2X
—
—
60
21
TioF
Port Output Fall Time
PIC18F6525/6621/
—
10
25
8525/8621
21A
PIC18LF6X2X/8X2X
—
—
60
† These parameters are asynchronous events not related to any internal clock edges.
Note 1: Measurements are taken in RC mode, where CLKO output is 4 x TOSC.
ns (Note 1)
ns (Note 1)
ns (Note 1)
ns (Note 1)
ns (Note 1)
ns (Note 1)
ns (Note 1)
ns
ns
ns
ns
ns
ns
ns
ns
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DS39612C-page 339