PIC18F6525_13 Datasheet, PDF (348/400 Pages) Microchip Technology – 64/80-Pin High-Performance, 64-Kbyte Enhanced Flash Microcontrollers with A/D

PIC18F6525/6621/8525/8621
TABLE 27-16: EXAMPLE SPI™ MODE REQUIREMENTS (MASTER MODE, CKE = 1)
Param.
No.
Symbol
Characteristic
Min
Max Units Conditions
71
TscH
71A
SCK Input High Time
(Slave mode)
Continuous
Single Byte
1.25 TCY + 30 —
40
—
72
TscL
72A
SCK Input Low Time
(Slave mode)
Continuous
Single Byte
1.25 TCY + 30 —
40
—
73
TdiV2scH, Setup Time of SDI Data Input to SCK Edge
TdiV2scL
100
—
73A
TB2B
Last Clock Edge of Byte 1 to the 1st Clock Edge of 1.5 TCY + 40 —
Byte 2
74
TscH2diL, Hold Time of SDI Data Input to SCK Edge
TscL2diL
100
—
75
TdoR
SDO Data Output Rise Time PIC18F6525/6621/
—
25
8525/8621
PIC18LF6X2X/8X2X
45
76
TdoF
SDO Data Output Fall Time
—
25
78
TscR
SCK Output Rise Time
PIC18F6525/6621/
—
25
(Master mode)
8525/8621
PIC18LF6X2X/8X2X
45
79
TscF
SCK Output Fall Time (Master mode)
—
25
80
TscH2doV, SDO Data Output Valid after PIC18F6525/6621/
—
50
TscL2doV SCK Edge
8525/8621
PIC18LF6X2X/8X2X
100
81
TdoV2scH, SDO Data Output Setup to SCK Edge
TdoV2scL
TCY
—
Note 1: Requires the use of Parameter #73A.
2: Only if Parameter #71A and #72A are used.
ns
ns (Note 1)
ns
ns (Note 1)
ns
ns (Note 2)
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
FIGURE 27-16: EXAMPLE SPI™ SLAVE MODE TIMING (CKE = 0)
SS
SCK
(CKP = 0)
SCK
(CKP = 1)
70
71
72
80
83
78
79
79
78
SDO
MSb
bit 6 - - - - - -1
LSb
SDI
Note:
75, 76
MSb In
bit 6 - - - -1
74
73
Refer to Figure 27-4 for load conditions.
77
LSb In
DS39612C-page 348
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