PIC18F6525_13 Datasheet, PDF (287/400 Pages) Microchip Technology – 64/80-Pin High-Performance, 64-Kbyte Enhanced Flash Microcontrollers with A/D

PIC18F6525/6621/8525/8621
BRA
Unconditional Branch
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Q Cycle Activity:
Q1
Decode
No
operation
[ label ] BRA n
-1024  n  1023
(PC) + 2 + 2n  PC
None
1101 0nnn nnnn nnnn
Add the 2’s complement number ‘2n’ to
the PC. Since the PC will have
incremented to fetch the next
instruction, the new address will be
PC + 2 + 2n. This instruction is a
two-cycle instruction.
1
2
Q2
Read literal
‘n’
No
operation
Q3
Process
Data
No
operation
Q4
Write to PC
No
operation
Example:
HERE
BRA Jump
Before Instruction
PC
=
After Instruction
PC
=
address (HERE)
address (Jump)
BSF
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Q Cycle Activity:
Q1
Decode
Bit Set f
[ label ] BSF f,b[,a]
0  f  255
0b7
a [0,1]
1  f<b>
None
1000 bbba ffff ffff
Bit ‘b’ in register ‘f’ is set. If ‘a’ is ‘0’,
Access Bank will be selected, over-
riding the BSR value. If ‘a’ = 1, then the
bank will be selected as per the BSR
value.
1
1
Q2
Read
register ‘f’
Q3
Process
Data
Q4
Write
register ‘f’
Example:
BSF
Before Instruction
FLAG_REG =
After Instruction
FLAG_REG =
FLAG_REG, 7, 1
0x0A
0x8A
 2003-2013 Microchip Technology Inc.
DS39612C-page 287