PIC18F6525_13 Datasheet, PDF (284/400 Pages) Microchip Technology – 64/80-Pin High-Performance, 64-Kbyte Enhanced Flash Microcontrollers with A/D

PIC18F6525/6621/8525/8621
BCF
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Q Cycle Activity:
Q1
Decode
Bit Clear f
[ label ] BCF
0  f  255
0b7
a [0,1]
0  f<b>
None
f,b[,a]
1001 bbba ffff ffff
Bit ‘b’ in register ‘f’ is cleared. If ‘a’ is ‘0’,
the Access Bank will be selected,
overriding the BSR value. If ‘a’ = 1, then
the bank will be selected as per the
BSR value (default).
1
1
Q2
Read
register ‘f’
Q3
Process
Data
Q4
Write
register ‘f’
Example:
BCF
Before Instruction
FLAG_REG =
After Instruction
FLAG_REG =
FLAG_REG, 7, 0
0xC7
0x47
BN
Branch if Negative
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Q Cycle Activity:
If Jump:
Q1
Decode
No
operation
If No Jump:
Q1
Decode
[ label ] BN n
-128  n  127
if Negative bit is ‘1’
(PC) + 2 + 2n  PC
None
1110 0110 nnnn nnnn
If the Negative bit is ‘1’, then the
program will branch.
The 2’s complement number ‘2n’ is
added to the PC. Since the PC will have
incremented to fetch the next
instruction, the new address will be
PC + 2 + 2n. This instruction is then a
two-cycle instruction.
1
1(2)
Q2
Read literal
‘n’
No
operation
Q3
Process
Data
No
operation
Q4
Write to PC
No
operation
Q2
Read literal
‘n’
Q3
Process
Data
Q4
No
operation
Example:
HERE
Before Instruction
PC
=
After Instruction
If Negative =
PC
=
If Negative =
PC
=
BN Jump
address (HERE)
1;
address (Jump)
0;
address (HERE + 2)
DS39612C-page 284
 2003-2013 Microchip Technology Inc.