PIC18F6525_13 Datasheet, PDF (28/400 Pages) Microchip Technology – 64/80-Pin High-Performance, 64-Kbyte Enhanced Flash Microcontrollers with A/D

PIC18F6525/6621/8525/8621
If the main oscillator is configured in the RC, RCIO, EC
or ECIO modes, there is no oscillator start-up time-out.
Operation will resume after eight cycles of the main
oscillator have been counted. A timing diagram, indi-
cating the transition from the Timer1 oscillator to the
main oscillator for RC, RCIO, EC and ECIO modes, is
shown in Figure 2-12.
FIGURE 2-12:
T1OSI
OSC1
TIMING FOR TRANSITION BETWEEN TIMER1 AND OSC1 (RC, EC)
Q3
Q4
Q1
TT1P
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
TOSC
12 34 5 6 7 8
Internal System
Clock
SCS
(OSCCON<0>)
Program
Counter
PC
Note: RC Oscillator mode assumed.
TSCS
PC + 2
PC + 4
2.7 Effects of Sleep Mode on the
On-Chip Oscillator
When the device executes a SLEEP instruction, the on-
chip clocks and oscillator are turned off and the device
is held at the beginning of an instruction cycle (Q1
state). With the oscillator off, the OSC1 and OSC2
signals will stop oscillating. Since all the transistor
switching currents have been removed, Sleep mode
achieves the lowest current consumption of the device
(only leakage currents). Enabling any on-chip feature
that will operate during Sleep will increase the current
consumed during Sleep. The user can wake from
Sleep through external Reset, Watchdog Timer Reset,
or through an interrupt.
TABLE 2-3: OSC1 AND OSC2 PIN STATES IN SLEEP MODE
Oscillator Mode
OSC1 Pin
OSC2 Pin
RC
RCIO
ECIO
EC
LP, XT and HS
Floating, external resistor should pull high
Floating, external resistor should pull high
Floating
Floating
Feedback inverter disabled at
quiescent voltage level
At logic low
Configured as PORTA, bit 6
Configured as PORTA, bit 6
At logic low
Feedback inverter disabled at
quiescent voltage level
Note: See Table 3-1 in Section 3.0 “Reset” for time-outs due to Sleep and MCLR Reset.
2.8 Power-up Delays
Power-up delays are controlled by two timers so that no
external Reset circuitry is required for most
applications. The delays ensure that the device is kept
in Reset until the device power supply and clock are
stable. For additional information on Reset operation,
see Section 3.0 “Reset”.
The first timer is the Power-up Timer (PWRT) which
optionally provides a fixed delay of 72 ms (nominal) on
power-up only (POR and BOR). The second timer is
the Oscillator Start-up Timer (OST), intended to keep
the chip in Reset until the crystal oscillator is stable.
With the PLL enabled (HS+PLL and EC+PLL oscillator
mode), the time-out sequence following a Power-on
Reset is different from other oscillator modes. The
time-out sequence is as follows: First, the PWRT time-
out is invoked after a POR time delay has expired.
Then, the Oscillator Start-up Timer (OST) is invoked.
However, this is still not a sufficient amount of time to
allow the PLL to lock at high frequencies. The PWRT
timer is used to provide an additional fixed 2 ms
(nominal) time-out to allow the PLL ample time to lock
to the incoming clock frequency.
DS39612C-page 28
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