PIC18F6525_13 Datasheet, PDF(181/400 Page) Microchip Technology – 64/80-Pin High-Performance, 64-Kbyte Enhanced Flash Microcontrollers with A/D

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PIC18F6525_13 Datasheet, PDF (181/400 Pages) Microchip Technology – 64/80-Pin High-Performance, 64-Kbyte Enhanced Flash Microcontrollers with A/D

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PIC18F6525/6621/8525/8621

18.3.8 SLEEP OPERATION

In Master mode, all module clocks are halted and the

transmission/reception will remain in that state until the

device wakes from Sleep. After the device returns to

normal mode, the module will continue to transmit/

receive data.

In Slave mode, the SPI Transmit/Receive Shift register

operates asynchronously to the device. This allows the

device to be placed in Sleep mode and data to be

shifted into the SPI Transmit/Receive Shift register.

When all 8 bits have been received, the MSSP interrupt

flag bit will be set and if enabled, will wake the device

from Sleep.

18.3.9 EFFECTS OF A RESET

A Reset disables the MSSP module and terminates the

current transfer.

18.3.10 BUS MODE COMPATIBILITY

Table 18-1 shows the compatibility between the

standard SPI modes and the states of the CKP and

CKE control bits.

TABLE 18-1: SPIâ¢ BUS MODES

Standard SPI Mode

Terminology

Control Bits State

CKP

CKE

0, 0

0

1

0, 1

0

0

1, 0

1

1

1, 1

1

0

There is also a SMP bit which controls when the data is

sampled.

TABLE 18-2: REGISTERS ASSOCIATED WITH SPIâ¢ OPERATION

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Value on

POR, BOR

Value on

all other

Resets

INTCON

PIR1

PIE1

IPR1

GIE/GIEH

PSPIF(1)

PSPIE(1)

PSPIP(1)

PEIE/GIEL

ADIF

ADIE

ADIP

TMR0IE

RC1IF

RC1IE

RC1IP

INT0IE

TX1IF

TX1IE

TX1IP

RBIE

SSPIF

SSPIE

SSPIP

TMR0IF

CCP1IF

CCP1IE

CCP1IP

INT0IF

TMR2IF

TMR2IE

TMR2IP

RBIF 0000 000x 0000 000u

TMR1IF 0000 0000 0000 0000

TMR1IE 0000 0000 0000 0000

TMR1IP 1111 1111 1111 1111

TRISC

PORTC Data Direction Register

1111 1111 1111 1111

TRISF

TRISF7 TRISF6 TRISF5 TRISF4 TRISF3 TRISF2 TRISF1 TRISF0 1111 1111 1111 1111

SSPBUF MSSP Receive Buffer/Transmit Register

xxxx xxxx uuuu uuuu

SSPCON1 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 0000 0000

SSPSTAT

SMP

CKE

D/A

P

S

R/W

UA

BF 0000 0000 0000 0000

Legend: x = unknown, u = unchanged, â = unimplemented, read as â0â. Shaded cells are not used by the MSSP in SPIâ¢ mode.

Note 1: Enabled only in Microcontroller mode for PIC18F8525/8621 devices.

ï£ 2003-2013 Microchip Technology Inc.

DS39612C-page 181

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