PIC18F6525_13 Datasheet, PDF(36/400 Page) Microchip Technology – 64/80-Pin High-Performance, 64-Kbyte Enhanced Flash Microcontrollers with A/D

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PIC18F6525_13 Datasheet, PDF (36/400 Pages) Microchip Technology – 64/80-Pin High-Performance, 64-Kbyte Enhanced Flash Microcontrollers with A/D

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PIC18F6525/6621/8525/8621

TABLE 3-3: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)

Register

Applicable Devices

Power-on Reset,

Brown-out Reset

MCLR Resets

WDT Reset

RESET Instruction

Stack Resets

Wake-up via WDT

or Interrupt

PORTG(7)

Feature1 Feature2

--xx xxxx

--uu uuuu

--uu uuuu

PORTF

Feature1 Feature2

x000 0000

u000 0000

uuuu uuuu

PORTE

Feature1 Feature2

xxxx xxxx

uuuu uuuu

uuuu uuuu

PORTD

Feature1 Feature2

xxxx xxxx

uuuu uuuu

uuuu uuuu

PORTC

Feature1 Feature2

xxxx xxxx

uuuu uuuu

uuuu uuuu

PORTB

PORTA(5,6)

Feature1

Feature1

Feature2

Feature2

xxxx xxxx

-x0x 0000(5)

uuuu uuuu

-u0u 0000(5)

uuuu uuuu

-uuu uuuu(5)

SPBRGH1

Feature1

Feature2

0000 0000

0000 0000

uuuu uuuu

BAUDCON1

Feature1

Feature2

-1-0 0-00

-1-0 0-00

-u-u u-uu

SPBRGH2

Feature1

Feature2

0000 0000

0000 0000

uuuu uuuu

BAUDCON2

Feature1

Feature2

-1-0 0-00

-1-0 0-00

-u-1 u-uu

ECCP1DEL

Feature1 Feature2

0000 0000

0000 0000

uuuu uuuu

TMR4

Feature1 Feature2

0000 0000

0000 0000

uuuu uuuu

PR4

Feature1 Feature2

1111 1111

1111 1111

uuuu uuuu

T4CON

Feature1 Feature2

-000 0000

-000 0000

-uuu uuuu

CCPR4H

Feature1 Feature2

xxxx xxxx

xxxx xxxx

uuuu uuuu

CCPR4L

Feature1 Feature2

xxxx xxxx

xxxx xxxx

uuuu uuuu

CCP4CON

Feature1 Feature2

--00 0000

--00 0000

--uu uuuu

CCPR5H

Feature1 Feature2

xxxx xxxx

xxxx xxxx

uuuu uuuu

CCPR5L

Feature1 Feature2

xxxx xxxx

xxxx xxxx

uuuu uuuu

CCP5CON

Feature1 Feature2

--00 0000

--00 0000

--uu uuuu

SPBRG2

Feature1 Feature2

0000 0000

0000 0000

uuuu uuuu

RCREG2

Feature1 Feature2

0000 0000

0000 0000

uuuu uuuu

TXREG2

Feature1 Feature2

0000 0000

0000 0000

uuuu uuuu

TXSTA2

Feature1 Feature2

0000 0010

0000 0010

uuuu uuuu

RCSTA2

Feature1 Feature2

0000 000x

0000 000x

uuuu uuuu

ECCP3AS

Feature1 Feature2

0000 0000

0000 0000

uuuu uuuu

ECCP3DEL

Feature1 Feature2

0000 0000

0000 0000

uuuu uuuu

ECCP2AS

Feature1 Feature2

0000 0000

0000 0000

uuuu uuuu

ECCP2DEL

Feature1 Feature2

0000 0000

0000 0000

uuuu uuuu

Legend:

Note 1:

2:

3:

4:

5:

6:

7:

8:

9:

u = unchanged, x = unknown, - = unimplemented bit, read as â0â, q = value depends on condition.

Shaded cells indicate conditions do not apply for the designated device.

One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).

When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt

vector (0008h or 0018h).

When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are

updated with the current value of the PC. The STKPTR is modified to point to the next location in the

hardware stack.

See Table 3-2 for Reset value for specific condition.

Bit 6 of PORTA, LATA and TRISA are enabled in ECIO and RCIO Oscillator modes only. In all other

oscillator modes, they are disabled and read â0â.

Bit 6 of PORTA, LATA and TRISA are not available on all devices. When unimplemented, they are read â0â.

If MCLR function is disabled, PORTG<5> is a read-only bit.

Enabled only in Microcontroller mode for PIC18F8525/8621 devices.

The MEMCON register is unimplemented and reads all â0âs when the device is in Microcontroller mode.

DS39612C-page 36

ï£ 2003-2013 Microchip Technology Inc.

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