PIC18F6525_13 Datasheet, PDF (107/400 Pages) Microchip Technology – 64/80-Pin High-Performance, 64-Kbyte Enhanced Flash Microcontrollers with A/D

PIC18F6525/6621/8525/8621
FIGURE 10-6:
BLOCK DIAGRAM OF RB2:RB0 PINS
RBPU⁽²⁾
Data Bus
WR LATB or
WR PORTB
WR TRISB
Data Latch
DQ
CK
TRIS Latch
DQ
CK
VDD
P
Weak
Pull-up
I/O pin⁽¹⁾
TTL
Input
Buffer
RD TRISB
RD PORTB
QD
EN
Note 1:
2:
INTx
Schmitt Trigger
Buffer
RD Port
I/O pins have diode protection to VDD and VSS.
To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit (INTCON2<7>).
FIGURE 10-7:
BLOCK DIAGRAM OF RB3 PIN
RBPU⁽²⁾
CCP2MX
ECCP Output⁽³⁾
1
Enable⁽³⁾
ECCP Output
Data Bus
WR LATB or
WR PORTB
WR TRISB
0
Data Latch
DQ
CK
TRIS Latch
D
CK _Q
VDD
P
Weak
Pull-up
VDD
P
N
VSS
TTL
Input
Buffer
I/O pin⁽¹⁾
RD TRISB
RD LATB
RD PORTB
Q
D
EN
RD PORTB
ECCP2 or INT3
Schmitt Trigger
Buffer
CCP2MX = 0
Note 1:
2:
3:
I/O pin has diode protection to VDD and VSS.
To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit (INTCON2<7>).
For PIC18F8525/8621 parts, the ECCP2 input/output is multiplexed with RB3 if the CCP2MX bit is enabled (= 0)
in the Configuration register and the device is operating in Microprocessor, Microprocessor with Boot Block or
Extended Microcontroller mode.
 2003-2013 Microchip Technology Inc.
DS39612C-page 107