PIC18F6525_13 Datasheet, PDF (20/400 Pages) Microchip Technology – 64/80-Pin High-Performance, 64-Kbyte Enhanced Flash Microcontrollers with A/D

PIC18F6525/6621/8525/8621
TABLE 1-2: PIC18F6525/6621/8525/8621 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name
Pin Number
PIC18F6X2X PIC18F8X2X
Pin
Type
Buffer
Type
Description
RJ0/ALE
RJ0
ALE
PORTJ is a bidirectional I/O port⁽⁶⁾.
—
62
I/O
ST
Digital I/O.
O
TTL
External memory address latch enable.
RJ1/OE
RJ1
OE
RJ2/WRL
RJ2
WRL
—
61
I/O
ST
Digital I/O.
O
TTL
External memory output enable.
—
60
I/O
ST
Digital I/O.
O
TTL
External memory write low control.
RJ3/WRH
RJ3
WRH
RJ4/BA0
RJ4
BA0
—
59
I/O
ST
Digital I/O.
O
TTL
External memory write high control.
—
39
I/O
ST
Digital I/O.
O
TTL
System bus byte address 0 control.
RJ5/CE
RJ5
CE
RJ6/LB
RJ6
LB
—
40
I/O
ST
Digital I/O
O
TTL
External memory access indicator.
—
41
I/O
ST
Digital I/O.
O
TTL
External memory low byte select.
RJ7/UB
RJ7
UB
VSS
—
9, 25,
41, 56
42
11, 31,
51, 70
I/O
ST
O
TTL
Digital I/O.
External memory high byte select.
P
— Ground reference for logic and I/O pins.
VDD
AVSS⁽⁸⁾
AVDD⁽⁸⁾
10, 26,
38, 57
20
19
12, 32,
48, 71
26
25
P
— Positive supply for logic and I/O pins.
P
— Ground reference for analog modules.
P
— Positive supply for analog modules.
Legend: TTL = TTL compatible input
CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels
Analog = Analog input
I = Input
O
= Output
P = Power
OD = Open-Drain (no P diode to VDD)
Note 1: Alternate assignment for ECCP2/P2A in PIC18F8525/8621 devices when CCP2MX (CONFIG3H<0>) is not set (all
Program Memory modes except Microcontroller).
2: Default assignment for ECCP2/P2A when CCP2MX is set (all devices).
3: External memory interface functions are only available on PIC18F8525/8621 devices.
4: Default assignment for P1B/P1C/P3B/P3C for PIC18F8525/8621 devices when ECCPMX (CONFIG3H<1>) is set and for
all PIC18F6525/6621 devices.
5: Alternate assignment for ECCP2/P2A in PIC18F8525/8621 devices when CCP2MX is not set (Microcontroller mode).
6: PORTH and PORTJ (and their multiplexed functions) are only available on PIC18F8525/8621 devices.
7: Alternate assignment for P1B/P1C/P3B/P3C for PIC18F8525/8621 devices when ECCPMX (CONFIG3H<1>) is not set.
8: AVDD must be connected to a positive supply and AVSS must be connected to a ground reference for proper operation of
the part in user or ICSP™ modes. See parameter D001 for details.
9: RG5 is multiplexed with MCLR and is only available when the MCLR Resets are disabled.
DS39612C-page 20
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