PIC18F6525_13 Datasheet, PDF (391/400 Pages) Microchip Technology – 64/80-Pin High-Performance, 64-Kbyte Enhanced Flash Microcontrollers with A/D

PIC18F6525/6621/8525/8621
CONFIG7H (Configuration 7 High) ........................... 266
CONFIG7L (Configuration 7 Low)............................. 265
CVRCON (Comparator Voltage
Reference Control) ........................................... 249
Device ID Register 2 ................................................. 266
DEVID1 (Device ID Register 1)................................. 266
ECCPxAS (ECCP Auto-Shutdown Control).............. 169
ECCPxDEL (PWM Configuration)............................. 168
EECON1 (Data EEPROM Control 1) .................... 63, 80
INTCON (Interrupt Control)......................................... 89
INTCON2 (Interrupt Control 2).................................... 90
INTCON3 (Interrupt Control 3).................................... 91
IPR1 (Peripheral Interrupt Priority 1)........................... 98
IPR2 (Peripheral Interrupt Priority 2)........................... 99
IPR3 (Peripheral Interrupt Priority 3)......................... 100
LVDCON (Low-Voltage Detect Control).................... 255
MEMCON (Memory Control)....................................... 71
OSCCON (Oscillator Control) ..................................... 25
PIE1 (Peripheral Interrupt Enable 1)........................... 95
PIE2 (Peripheral Interrupt Enable 2)........................... 96
PIE3 (Peripheral Interrupt Enable 3)........................... 97
PIR1 (Peripheral Interrupt
Request (Flag) 1) ................................................ 92
PIR2 (Peripheral Interrupt
Request (Flag) 2) ................................................ 93
PIR3 (Peripheral Interrupt
Request (Flag) 3) ................................................ 94
PSPCON (Parallel Slave Port Control) ..................... 129
RCON (Reset Control) ........................................ 59, 101
RCSTAx (Receive Status and Control)..................... 215
SSPCON1 (MSSP Control 1, I²C Mode) .................. 184
SSPCON1 (MSSP Control 1, SPI Mode).................. 175
SSPCON2 (MSSP Control 2, I²C Mode) .................. 185
SSPSTAT (MSSP Status, I²C Mode)........................ 183
SSPSTAT (MSSP Status, SPI Mode) ....................... 174
STATUS...................................................................... 58
STKPTR (Stack Pointer) ............................................. 43
Summary............................................................... 51–54
T0CON (Timer0 Control)........................................... 131
T1CON (Timer 1 Control).......................................... 135
T2CON (Timer 2 Control).......................................... 141
T3CON (Timer3 Control)........................................... 143
T4CON (Timer 4 Control).......................................... 147
TXSTAx (Transmit Status and Control) .................... 214
WDTCON (Watchdog Timer Control) ....................... 267
RESET .............................................................................. 305
Reset........................................................................... 29, 259
MCLR Reset (normal operation) ................................. 29
MCLR Reset (Sleep)................................................... 29
Power-on Reset .......................................................... 29
Programmable Brown-out Reset (BOR) ..................... 29
RESET Instruction ...................................................... 29
Stack Full Reset.......................................................... 29
Stack Underflow Reset ............................................... 29
Watchdog Timer (WDT) Reset.................................... 29
RETFIE ............................................................................. 306
RETLW ............................................................................. 306
RETURN ........................................................................... 307
Return Address Stack ......................................................... 42
and Associated Registers ........................................... 43
Revision History ................................................................ 377
RLCF................................................................................. 307
RLNCF .............................................................................. 308
RRCF ................................................................................ 308
RRNCF ............................................................................. 309
S
SCK .................................................................................. 173
SDI.................................................................................... 173
SDO .................................................................................. 173
Serial Clock, SCK ............................................................. 173
Serial Data In (SDI)........................................................... 173
Serial Data Out (SDO) ...................................................... 173
Serial Peripheral Interface. See SPI Mode.
SETF ................................................................................ 309
Slave Select (SS).............................................................. 173
Slave Select Synchronization ........................................... 179
SLEEP .............................................................................. 310
Sleep ........................................................................ 259, 269
Software Simulator (MPLAB SIM) .................................... 318
Software Simulator (MPLAB SIM30) ................................ 318
Special Event Trigger. See Compare (ECCP Mode).
Special Event Trigger. See Compare (ECCP Module).
Special Features of the CPU ............................................ 259
Configuration Registers .................................... 260–266
Special Function Registers ................................................. 47
Map............................................................................. 49
SPI Mode
Associated Registers................................................ 181
Bus Mode Compatibility ............................................ 181
Effects of a Reset ..................................................... 181
Master Mode............................................................. 178
Master/Slave Connection ......................................... 177
Serial Clock .............................................................. 173
Serial Data In............................................................ 173
Serial Data Out ......................................................... 173
Slave Mode............................................................... 179
Slave Select.............................................................. 173
Slave Select Synchronization ................................... 179
Sleep Operation........................................................ 181
SPI Clock.................................................................. 178
SS ..................................................................................... 173
SSPOV ............................................................................. 203
SSPOV Status Flag .......................................................... 203
SSPSTAT Register
R/W Bit ............................................................. 186, 187
Status Bits
Significance and Initialization Condition
for RCON Register ............................................. 31
SUBFWB .......................................................................... 310
SUBLW ............................................................................. 311
SUBWF............................................................................. 311
SUBWFB .......................................................................... 312
SWAPF ............................................................................. 312
T
T0CON Register
PSA Bit ..................................................................... 133
T0CS Bit ................................................................... 133
T0PS2:T0PS0 Bits.................................................... 133
T0SE Bit ................................................................... 133
Table Pointer Operations (table)......................................... 64
TBLRD .............................................................................. 313
TBLWT ............................................................................. 314
Time-out in Various Situations............................................ 31
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DS39612C-page 391